configs/example/memcheck.py

   1 # Copyright (c) 2015-2016 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
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  13 # Copyright (c) 2006-2007 The Regents of The University of Michigan
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  38
  39 from __future__ import print_function
  40 from __future__ import absolute_import
  41
  42 import optparse
  43 import random
  44 import sys
  45
  46 import m5
  47 from m5.objects import *
  48
  49 parser = optparse.OptionParser()
  50
  51 parser.add_option("-a", "--atomic", action="store_true",
  52                   help="Use atomic (non-timing) mode")
  53 parser.add_option("-b", "--blocking", action="store_true",
  54                   help="Use blocking caches")
  55 parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
  56                   metavar="T",
  57                   help="Stop after T ticks")
  58 parser.add_option("-p", "--prefetchers", action="store_true",
  59                   help="Use prefetchers")
  60 parser.add_option("-s", "--stridepref", action="store_true",
  61                   help="Use strided prefetchers")
  62
  63 # This example script has a lot in common with the memtest.py in that
  64 # it is designed to stress tests the memory system. However, this
  65 # script uses oblivious traffic generators to create the stimuli, and
  66 # couples them with memcheckers to verify that the data read matches
  67 # the allowed outcomes. Just like memtest.py, the traffic generators
  68 # and checkers are placed in a tree topology. At the bottom of the
  69 # tree is a shared memory, and then at each level a number of
  70 # generators and checkers are attached, along with a number of caches
  71 # that them selves fan out to subtrees of generators and caches. Thus,
  72 # it is possible to create a system with arbitrarily deep cache
  73 # hierarchies, sharing or no sharing of caches, and generators not
  74 # only at the L1s, but also at the L2s, L3s etc.
  75 #
  76 # The tree specification consists of two colon-separated lists of one
  77 # or more integers, one for the caches, and one for the
  78 # testers/generators. The first integer is the number of
  79 # caches/testers closest to main memory. Each cache then fans out to a
  80 # subtree. The last integer in the list is the number of
  81 # caches/testers associated with the uppermost level of memory. The
  82 # other integers (if any) specify the number of caches/testers
  83 # connected at each level of the crossbar hierarchy. The tester string
  84 # should have one element more than the cache string as there should
  85 # always be testers attached to the uppermost caches.
  86 #
  87 # Since this script tests actual sharing, there is also a possibility
  88 # to stress prefetching and the interaction between prefetchers and
  89 # caches. The traffic generators switch between random address streams
  90 # and linear address streams to ensure that the prefetchers will
  91 # trigger. By default prefetchers are off.
  92
  93 parser.add_option("-c", "--caches", type="string", default="3:2",
  94                   help="Colon-separated cache hierarchy specification, "
  95                   "see script comments for details "
  96                   "[default: %default]")
  97 parser.add_option("-t", "--testers", type="string", default="1:0:2",
  98                   help="Colon-separated tester hierarchy specification, "
  99                   "see script comments for details "
 100                   "[default: %default]")
 101 parser.add_option("-r", "--random", action="store_true",
 102                   help="Generate a random tree topology")
 103 parser.add_option("--sys-clock", action="store", type="string",
 104                   default='1GHz',
 105                   help = """Top-level clock for blocks running at system
 106                   speed""")
 107
 108 (options, args) = parser.parse_args()
 109
 110 if args:
 111      print("Error: script doesn't take any positional arguments")
 112      sys.exit(1)
 113
 114 # Start by parsing the command line options and do some basic sanity
 115 # checking
 116 if options.random:
 117      # Generate a tree with a valid number of testers
 118      tree_depth = random.randint(1, 4)
 119      cachespec = [random.randint(1, 3) for i in range(tree_depth)]
 120      testerspec = [random.randint(1, 3) for i in range(tree_depth + 1)]
 121      print("Generated random tree -c", ':'.join(map(str, cachespec)),
 122          "-t", ':'.join(map(str, testerspec)))
 123 else:
 124      try:
 125           cachespec = [int(x) for x in options.caches.split(':')]
 126           testerspec = [int(x) for x in options.testers.split(':')]
 127      except:
 128           print("Error: Unable to parse caches or testers option")
 129           sys.exit(1)
 130
 131      if len(cachespec) < 1:
 132           print("Error: Must have at least one level of caches")
 133           sys.exit(1)
 134
 135      if len(cachespec) != len(testerspec) - 1:
 136           print("Error: Testers must have one element more than caches")
 137           sys.exit(1)
 138
 139      if testerspec[-1] == 0:
 140           print("Error: Must have testers at the uppermost level")
 141           sys.exit(1)
 142
 143      for t in testerspec:
 144           if t < 0:
 145                print("Error: Cannot have a negative number of testers")
 146                sys.exit(1)
 147
 148      for c in cachespec:
 149           if c < 1:
 150                print("Error: Must have 1 or more caches at each level")
 151                sys.exit(1)
 152
 153 # Determine the tester multiplier for each level as the string
 154 # elements are per subsystem and it fans out
 155 multiplier = [1]
 156 for c in cachespec:
 157      if c < 1:
 158           print("Error: Must have at least one cache per level")
 159      multiplier.append(multiplier[-1] * c)
 160
 161 numtesters = 0
 162 for t, m in zip(testerspec, multiplier):
 163      numtesters += t * m
 164
 165 # Define a prototype L1 cache that we scale for all successive levels
 166 proto_l1 = Cache(size = '32kB', assoc = 4,
 167                  tag_latency = 1, data_latency = 1, response_latency = 1,
 168                  tgts_per_mshr = 8)
 169
 170 if options.blocking:
 171      proto_l1.mshrs = 1
 172 else:
 173      proto_l1.mshrs = 4
 174
 175 if options.prefetchers:
 176      proto_l1.prefetcher = TaggedPrefetcher()
 177 elif options.stridepref:
 178      proto_l1.prefetcher = StridePrefetcher()
 179
 180 cache_proto = [proto_l1]
 181
 182 # Now add additional cache levels (if any) by scaling L1 params, the
 183 # first element is Ln, and the last element L1
 184 for scale in cachespec[:-1]:
 185      # Clone previous level and update params
 186      prev = cache_proto[0]
 187      next = prev()
 188      next.size = prev.size * scale
 189      next.tag_latency = prev.tag_latency * 10
 190      next.data_latency = prev.data_latency * 10
 191      next.response_latency = prev.response_latency * 10
 192      next.assoc = prev.assoc * scale
 193      next.mshrs = prev.mshrs * scale
 194      cache_proto.insert(0, next)
 195
 196 # Create a config to be used by all the traffic generators
 197 cfg_file_name = "memcheck.cfg"
 198 cfg_file_path = os.path.dirname(__file__) + "/" +cfg_file_name
 199 cfg_file = open(cfg_file_path, 'w')
 200
 201 # Three states, with random, linear and idle behaviours. The random
 202 # and linear states access memory in the range [0 : 16 Mbyte] with 8
 203 # byte and 64 byte accesses respectively.
 204 cfg_file.write("STATE 0 10000000 RANDOM 65 0 16777216 8 50000 150000 0\n")
 205 cfg_file.write("STATE 1 10000000 LINEAR 65 0 16777216 64 50000 150000 0\n")
 206 cfg_file.write("STATE 2 10000000 IDLE\n")
 207 cfg_file.write("INIT 0\n")
 208 cfg_file.write("TRANSITION 0 1 0.5\n")
 209 cfg_file.write("TRANSITION 0 2 0.5\n")
 210 cfg_file.write("TRANSITION 1 0 0.5\n")
 211 cfg_file.write("TRANSITION 1 2 0.5\n")
 212 cfg_file.write("TRANSITION 2 0 0.5\n")
 213 cfg_file.write("TRANSITION 2 1 0.5\n")
 214 cfg_file.close()
 215
 216 # Make a prototype for the tester to be used throughout
 217 proto_tester = TrafficGen(config_file = cfg_file_path)
 218
 219 # Set up the system along with a DRAM controller
 220 system = System(physmem = DRAMCtrl(dram = DDR3_1600_8x8()))
 221
 222 system.voltage_domain = VoltageDomain(voltage = '1V')
 223
 224 system.clk_domain = SrcClockDomain(clock =  options.sys_clock,
 225                         voltage_domain = system.voltage_domain)
 226
 227 system.memchecker = MemChecker()
 228
 229 # For each level, track the next subsys index to use
 230 next_subsys_index = [0] * (len(cachespec) + 1)
 231
 232 # Recursive function to create a sub-tree of the cache and tester
 233 # hierarchy
 234 def make_cache_level(ncaches, prototypes, level, next_cache):
 235      global next_subsys_index, proto_l1, testerspec, proto_tester
 236
 237      index = next_subsys_index[level]
 238      next_subsys_index[level] += 1
 239
 240      # Create a subsystem to contain the crossbar and caches, and
 241      # any testers
 242      subsys = SubSystem()
 243      setattr(system, 'l%dsubsys%d' % (level, index), subsys)
 244
 245      # The levels are indexing backwards through the list
 246      ntesters = testerspec[len(cachespec) - level]
 247
 248      testers = [proto_tester() for i in range(ntesters)]
 249      checkers = [MemCheckerMonitor(memchecker = system.memchecker) \
 250                       for i in range(ntesters)]
 251      if ntesters:
 252           subsys.tester = testers
 253           subsys.checkers = checkers
 254
 255      if level != 0:
 256           # Create a crossbar and add it to the subsystem, note that
 257           # we do this even with a single element on this level
 258           xbar = L2XBar(width = 32)
 259           subsys.xbar = xbar
 260           if next_cache:
 261                xbar.master = next_cache.cpu_side
 262
 263           # Create and connect the caches, both the ones fanning out
 264           # to create the tree, and the ones used to connect testers
 265           # on this level
 266           tree_caches = [prototypes[0]() for i in range(ncaches[0])]
 267           tester_caches = [proto_l1() for i in range(ntesters)]
 268
 269           subsys.cache = tester_caches + tree_caches
 270           for cache in tree_caches:
 271                cache.mem_side = xbar.slave
 272                make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache)
 273           for tester, checker, cache in zip(testers, checkers, tester_caches):
 274                tester.port = checker.slave
 275                checker.master = cache.cpu_side
 276                cache.mem_side = xbar.slave
 277      else:
 278           if not next_cache:
 279                print("Error: No next-level cache at top level")
 280                sys.exit(1)
 281
 282           if ntesters > 1:
 283                # Create a crossbar and add it to the subsystem
 284                xbar = L2XBar(width = 32)
 285                subsys.xbar = xbar
 286                xbar.master = next_cache.cpu_side
 287                for tester, checker in zip(testers, checkers):
 288                     tester.port = checker.slave
 289                     checker.master = xbar.slave
 290           else:
 291                # Single tester
 292                testers[0].port = checkers[0].slave
 293                checkers[0].master = next_cache.cpu_side
 294
 295 # Top level call to create the cache hierarchy, bottom up
 296 make_cache_level(cachespec, cache_proto, len(cachespec), None)
 297
 298 # Connect the lowest level crossbar to the memory
 299 last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec))
 300 last_subsys.xbar.master = system.physmem.port
 301 last_subsys.xbar.point_of_coherency = True
 302
 303 root = Root(full_system = False, system = system)
 304 if options.atomic:
 305     root.system.mem_mode = 'atomic'
 306 else:
 307     root.system.mem_mode = 'timing'
 308
 309 # The system port is never used in the tester so merely connect it
 310 # to avoid problems
 311 root.system.system_port = last_subsys.xbar.slave
 312
 313 # Instantiate configuration
 314 m5.instantiate()
 315
 316 # Simulate until program terminates
 317 exit_event = m5.simulate(options.maxtick)
 318
 319 print('Exiting @ tick', m5.curTick(), 'because', exit_event.getCause())