mem: Add explicit Cache subclass and make BaseCache abstract
[gem5.git] / configs / example / memtest.py
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39 # Authors: Ron Dreslinski
40 # Andreas Hansson
41
42 import optparse
43 import random
44 import sys
45
46 import m5
47 from m5.objects import *
48
49 # This example script stress tests the memory system by creating false
50 # sharing in a tree topology. At the bottom of the tree is a shared
51 # memory, and then at each level a number of testers are attached,
52 # along with a number of caches that them selves fan out to subtrees
53 # of testers and caches. Thus, it is possible to create a system with
54 # arbitrarily deep cache hierarchies, sharing or no sharing of caches,
55 # and testers not only at the L1s, but also at the L2s, L3s etc.
56
57 parser = optparse.OptionParser()
58
59 parser.add_option("-a", "--atomic", action="store_true",
60 help="Use atomic (non-timing) mode")
61 parser.add_option("-b", "--blocking", action="store_true",
62 help="Use blocking caches")
63 parser.add_option("-l", "--maxloads", metavar="N", default=0,
64 help="Stop after N loads")
65 parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
66 metavar="T",
67 help="Stop after T ticks")
68
69 # The tree specification consists of two colon-separated lists of one
70 # or more integers, one for the caches, and one for the testers. The
71 # first integer is the number of caches/testers closest to main
72 # memory. Each cache then fans out to a subtree. The last integer in
73 # the list is the number of caches/testers associated with the
74 # uppermost level of memory. The other integers (if any) specify the
75 # number of caches/testers connected at each level of the crossbar
76 # hierarchy. The tester string should have one element more than the
77 # cache string as there should always be testers attached to the
78 # uppermost caches.
79
80 parser.add_option("-c", "--caches", type="string", default="2:2:1",
81 help="Colon-separated cache hierarchy specification, "
82 "see script comments for details "
83 "[default: %default]")
84 parser.add_option("-t", "--testers", type="string", default="1:1:0:2",
85 help="Colon-separated tester hierarchy specification, "
86 "see script comments for details "
87 "[default: %default]")
88 parser.add_option("-f", "--functional", type="int", default=0,
89 metavar="PCT",
90 help="Target percentage of functional accesses "
91 "[default: %default]")
92 parser.add_option("-u", "--uncacheable", type="int", default=0,
93 metavar="PCT",
94 help="Target percentage of uncacheable accesses "
95 "[default: %default]")
96 parser.add_option("-r", "--random", action="store_true",
97 help="Generate a random tree topology")
98 parser.add_option("--progress", type="int", default=100000,
99 metavar="NLOADS",
100 help="Progress message interval "
101 "[default: %default]")
102 parser.add_option("--sys-clock", action="store", type="string",
103 default='1GHz',
104 help = """Top-level clock for blocks running at system
105 speed""")
106
107 (options, args) = parser.parse_args()
108
109 if args:
110 print "Error: script doesn't take any positional arguments"
111 sys.exit(1)
112
113 # Get the total number of testers
114 def numtesters(cachespec, testerspec):
115 # Determine the tester multiplier for each level as the
116 # elements are per subsystem and it fans out
117 multiplier = [1]
118 for c in cachespec:
119 multiplier.append(multiplier[-1] * c)
120
121 total = 0
122 for t, m in zip(testerspec, multiplier):
123 total += t * m
124
125 return total
126
127 block_size = 64
128
129 # Start by parsing the command line options and do some basic sanity
130 # checking
131 if options.random:
132 # Generate a tree with a valid number of testers
133 while True:
134 tree_depth = random.randint(1, 4)
135 cachespec = [random.randint(1, 3) for i in range(tree_depth)]
136 testerspec = [random.randint(1, 3) for i in range(tree_depth + 1)]
137 if numtesters(cachespec, testerspec) < block_size:
138 break
139
140 print "Generated random tree -c", ':'.join(map(str, cachespec)), \
141 "-t", ':'.join(map(str, testerspec))
142 else:
143 try:
144 cachespec = [int(x) for x in options.caches.split(':')]
145 testerspec = [int(x) for x in options.testers.split(':')]
146 except:
147 print "Error: Unable to parse caches or testers option"
148 sys.exit(1)
149
150 if len(cachespec) < 1:
151 print "Error: Must have at least one level of caches"
152 sys.exit(1)
153
154 if len(cachespec) != len(testerspec) - 1:
155 print "Error: Testers must have one element more than caches"
156 sys.exit(1)
157
158 if testerspec[-1] == 0:
159 print "Error: Must have testers at the uppermost level"
160 sys.exit(1)
161
162 for t in testerspec:
163 if t < 0:
164 print "Error: Cannot have a negative number of testers"
165 sys.exit(1)
166
167 for c in cachespec:
168 if c < 1:
169 print "Error: Must have 1 or more caches at each level"
170 sys.exit(1)
171
172 if numtesters(cachespec, testerspec) > block_size:
173 print "Error: Limited to %s testers because of false sharing" \
174 % (block_size)
175 sys.exit(1)
176
177 # Define a prototype L1 cache that we scale for all successive levels
178 proto_l1 = Cache(size = '32kB', assoc = 4,
179 hit_latency = 1, response_latency = 1,
180 tgts_per_mshr = 8)
181
182 if options.blocking:
183 proto_l1.mshrs = 1
184 else:
185 proto_l1.mshrs = 4
186
187 cache_proto = [proto_l1]
188
189 # Now add additional cache levels (if any) by scaling L1 params, the
190 # first element is Ln, and the last element L1
191 for scale in cachespec[:-1]:
192 # Clone previous level and update params
193 prev = cache_proto[0]
194 next = prev()
195 next.size = prev.size * scale
196 next.hit_latency = prev.hit_latency * 10
197 next.response_latency = prev.response_latency * 10
198 next.assoc = prev.assoc * scale
199 next.mshrs = prev.mshrs * scale
200 cache_proto.insert(0, next)
201
202 # Make a prototype for the tester to be used throughout
203 proto_tester = MemTest(max_loads = options.maxloads,
204 percent_functional = options.functional,
205 percent_uncacheable = options.uncacheable,
206 progress_interval = options.progress)
207
208 # Set up the system along with a simple memory and reference memory
209 system = System(physmem = SimpleMemory(),
210 cache_line_size = block_size)
211
212 system.voltage_domain = VoltageDomain(voltage = '1V')
213
214 system.clk_domain = SrcClockDomain(clock = options.sys_clock,
215 voltage_domain = system.voltage_domain)
216
217 # For each level, track the next subsys index to use
218 next_subsys_index = [0] * (len(cachespec) + 1)
219
220 # Recursive function to create a sub-tree of the cache and tester
221 # hierarchy
222 def make_cache_level(ncaches, prototypes, level, next_cache):
223 global next_subsys_index, proto_l1, testerspec, proto_tester
224
225 index = next_subsys_index[level]
226 next_subsys_index[level] += 1
227
228 # Create a subsystem to contain the crossbar and caches, and
229 # any testers
230 subsys = SubSystem()
231 setattr(system, 'l%dsubsys%d' % (level, index), subsys)
232
233 # The levels are indexing backwards through the list
234 ntesters = testerspec[len(cachespec) - level]
235
236 # Scale the progress threshold as testers higher up in the tree
237 # (smaller level) get a smaller portion of the overall bandwidth,
238 # and also make the interval of packet injection longer for the
239 # testers closer to the memory (larger level) to prevent them
240 # hogging all the bandwidth
241 limit = (len(cachespec) - level + 1) * 100000000
242 testers = [proto_tester(interval = 10 * (level * level + 1),
243 progress_check = limit) \
244 for i in xrange(ntesters)]
245 if ntesters:
246 subsys.tester = testers
247
248 if level != 0:
249 # Create a crossbar and add it to the subsystem, note that
250 # we do this even with a single element on this level
251 xbar = L2XBar()
252 subsys.xbar = xbar
253 if next_cache:
254 xbar.master = next_cache.cpu_side
255
256 # Create and connect the caches, both the ones fanning out
257 # to create the tree, and the ones used to connect testers
258 # on this level
259 tree_caches = [prototypes[0]() for i in xrange(ncaches[0])]
260 tester_caches = [proto_l1() for i in xrange(ntesters)]
261
262 subsys.cache = tester_caches + tree_caches
263 for cache in tree_caches:
264 cache.mem_side = xbar.slave
265 make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache)
266 for tester, cache in zip(testers, tester_caches):
267 tester.port = cache.cpu_side
268 cache.mem_side = xbar.slave
269 else:
270 if not next_cache:
271 print "Error: No next-level cache at top level"
272 sys.exit(1)
273
274 if ntesters > 1:
275 # Create a crossbar and add it to the subsystem
276 xbar = L2XBar()
277 subsys.xbar = xbar
278 xbar.master = next_cache.cpu_side
279 for tester in testers:
280 tester.port = xbar.slave
281 else:
282 # Single tester
283 testers[0].port = next_cache.cpu_side
284
285 # Top level call to create the cache hierarchy, bottom up
286 make_cache_level(cachespec, cache_proto, len(cachespec), None)
287
288 # Connect the lowest level crossbar to the memory
289 last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec))
290 last_subsys.xbar.master = system.physmem.port
291
292 root = Root(full_system = False, system = system)
293 if options.atomic:
294 root.system.mem_mode = 'atomic'
295 else:
296 root.system.mem_mode = 'timing'
297
298 # The system port is never used in the tester so merely connect it
299 # to avoid problems
300 root.system.system_port = last_subsys.xbar.slave
301
302 # Instantiate configuration
303 m5.instantiate()
304
305 # Simulate until program terminates
306 exit_event = m5.simulate(options.maxtick)
307
308 print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()