rubytest: seperated read and write ports.
[gem5.git] / configs / example / memtest.py
1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
2 # All rights reserved.
3 #
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
6 # met: redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer;
8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution;
11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
14 #
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 #
27 # Authors: Ron Dreslinski
28
29 import optparse
30 import sys
31
32 import m5
33 from m5.objects import *
34
35 parser = optparse.OptionParser()
36
37 parser.add_option("-a", "--atomic", action="store_true",
38 help="Use atomic (non-timing) mode")
39 parser.add_option("-b", "--blocking", action="store_true",
40 help="Use blocking caches")
41 parser.add_option("-l", "--maxloads", metavar="N", default=0,
42 help="Stop after N loads")
43 parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
44 metavar="T",
45 help="Stop after T ticks")
46
47 #
48 # The "tree" specification is a colon-separated list of one or more
49 # integers. The first integer is the number of caches/testers
50 # connected directly to main memory. The last integer in the list is
51 # the number of testers associated with the uppermost level of memory
52 # (L1 cache, if there are caches, or main memory if no caches). Thus
53 # if there is only one integer, there are no caches, and the integer
54 # specifies the number of testers connected directly to main memory.
55 # The other integers (if any) specify the number of caches at each
56 # level of the hierarchy between.
57 #
58 # Examples:
59 #
60 # "2:1" Two caches connected to memory with a single tester behind each
61 # (single-level hierarchy, two testers total)
62 #
63 # "2:2:1" Two-level hierarchy, 2 L1s behind each of 2 L2s, 4 testers total
64 #
65 parser.add_option("-t", "--treespec", type="string", default="8:1",
66 help="Colon-separated multilevel tree specification, "
67 "see script comments for details "
68 "[default: %default]")
69
70 parser.add_option("--force-bus", action="store_true",
71 help="Use bus between levels even with single cache")
72
73 parser.add_option("-f", "--functional", type="int", default=0,
74 metavar="PCT",
75 help="Target percentage of functional accesses "
76 "[default: %default]")
77 parser.add_option("-u", "--uncacheable", type="int", default=0,
78 metavar="PCT",
79 help="Target percentage of uncacheable accesses "
80 "[default: %default]")
81
82 parser.add_option("--progress", type="int", default=1000,
83 metavar="NLOADS",
84 help="Progress message interval "
85 "[default: %default]")
86
87 (options, args) = parser.parse_args()
88
89 if args:
90 print "Error: script doesn't take any positional arguments"
91 sys.exit(1)
92
93 block_size = 64
94
95 try:
96 treespec = [int(x) for x in options.treespec.split(':')]
97 numtesters = reduce(lambda x,y: x*y, treespec)
98 except:
99 print "Error parsing treespec option"
100 sys.exit(1)
101
102 if numtesters > block_size:
103 print "Error: Number of testers limited to %s because of false sharing" \
104 % (block_size)
105 sys.exit(1)
106
107 if len(treespec) < 1:
108 print "Error parsing treespec"
109 sys.exit(1)
110
111 # define prototype L1 cache
112 proto_l1 = BaseCache(size = '32kB', assoc = 4, block_size = block_size,
113 latency = '1ns', tgts_per_mshr = 8)
114
115 if options.blocking:
116 proto_l1.mshrs = 1
117 else:
118 proto_l1.mshrs = 4
119
120 # build a list of prototypes, one for each level of treespec, starting
121 # at the end (last entry is tester objects)
122 prototypes = [ MemTest(atomic=options.atomic, max_loads=options.maxloads,
123 percent_functional=options.functional,
124 percent_uncacheable=options.uncacheable,
125 progress_interval=options.progress) ]
126
127 # next comes L1 cache, if any
128 if len(treespec) > 1:
129 prototypes.insert(0, proto_l1)
130
131 # now add additional cache levels (if any) by scaling L1 params
132 for scale in treespec[:-2]:
133 # clone previous level and update params
134 prev = prototypes[0]
135 next = prev()
136 next.size = prev.size * scale
137 next.latency = prev.latency * 10
138 next.assoc = prev.assoc * scale
139 next.mshrs = prev.mshrs * scale
140 prototypes.insert(0, next)
141
142 # system simulated
143 system = System(funcmem = SimpleMemory(in_addr_map = False),
144 physmem = SimpleMemory(latency = "100ns"))
145
146 def make_level(spec, prototypes, attach_obj, attach_port):
147 fanout = spec[0]
148 parent = attach_obj # use attach obj as config parent too
149 if len(spec) > 1 and (fanout > 1 or options.force_bus):
150 port = getattr(attach_obj, attach_port)
151 new_bus = Bus(clock="500MHz", width=16)
152 if (port.role == 'MASTER'):
153 new_bus.slave = port
154 attach_port = "master"
155 else:
156 new_bus.master = port
157 attach_port = "slave"
158 parent.cpu_side_bus = new_bus
159 attach_obj = new_bus
160 objs = [prototypes[0]() for i in xrange(fanout)]
161 if len(spec) > 1:
162 # we just built caches, more levels to go
163 parent.cache = objs
164 for cache in objs:
165 cache.mem_side = getattr(attach_obj, attach_port)
166 make_level(spec[1:], prototypes[1:], cache, "cpu_side")
167 else:
168 # we just built the MemTest objects
169 parent.cpu = objs
170 for t in objs:
171 t.test = getattr(attach_obj, attach_port)
172 t.functional = system.funcmem.port
173
174 make_level(treespec, prototypes, system.physmem, "port")
175
176 # -----------------------
177 # run simulation
178 # -----------------------
179
180 root = Root( full_system = False, system = system )
181 if options.atomic:
182 root.system.mem_mode = 'atomic'
183 else:
184 root.system.mem_mode = 'timing'
185
186 # The system port is never used in the tester so merely connect it
187 # to avoid problems
188 root.system.system_port = root.system.physmem.port
189
190 # Not much point in this being higher than the L1 latency
191 m5.ticks.setGlobalFrequency('1ns')
192
193 # instantiate configuration
194 m5.instantiate()
195
196 # simulate until program terminates
197 exit_event = m5.simulate(options.maxtick)
198
199 print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()