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39 # Authors: Ron Dreslinski
47 from m5
.objects
import *
49 # This example script stress tests the memory system by creating false
50 # sharing in a tree topology. At the bottom of the tree is a shared
51 # memory, and then at each level a number of testers are attached,
52 # along with a number of caches that them selves fan out to subtrees
53 # of testers and caches. Thus, it is possible to create a system with
54 # arbitrarily deep cache hierarchies, sharing or no sharing of caches,
55 # and testers not only at the L1s, but also at the L2s, L3s etc.
57 parser
= optparse
.OptionParser()
59 parser
.add_option("-a", "--atomic", action
="store_true",
60 help="Use atomic (non-timing) mode")
61 parser
.add_option("-b", "--blocking", action
="store_true",
62 help="Use blocking caches")
63 parser
.add_option("-l", "--maxloads", metavar
="N", default
=0,
64 help="Stop after N loads")
65 parser
.add_option("-m", "--maxtick", type="int", default
=m5
.MaxTick
,
67 help="Stop after T ticks")
69 # The tree specification consists of two colon-separated lists of one
70 # or more integers, one for the caches, and one for the testers. The
71 # first integer is the number of caches/testers closest to main
72 # memory. Each cache then fans out to a subtree. The last integer in
73 # the list is the number of caches/testers associated with the
74 # uppermost level of memory. The other integers (if any) specify the
75 # number of caches/testers connected at each level of the crossbar
76 # hierarchy. The tester string should have one element more than the
77 # cache string as there should always be testers attached to the
80 parser
.add_option("-c", "--caches", type="string", default
="2:2:1",
81 help="Colon-separated cache hierarchy specification, "
82 "see script comments for details "
83 "[default: %default]")
84 parser
.add_option("-t", "--testers", type="string", default
="1:1:0:2",
85 help="Colon-separated tester hierarchy specification, "
86 "see script comments for details "
87 "[default: %default]")
88 parser
.add_option("-f", "--functional", type="int", default
=10,
90 help="Target percentage of functional accesses "
91 "[default: %default]")
92 parser
.add_option("-u", "--uncacheable", type="int", default
=10,
94 help="Target percentage of uncacheable accesses "
95 "[default: %default]")
96 parser
.add_option("-r", "--random", action
="store_true",
97 help="Generate a random tree topology")
98 parser
.add_option("--progress", type="int", default
=100000,
100 help="Progress message interval "
101 "[default: %default]")
102 parser
.add_option("--sys-clock", action
="store", type="string",
104 help = """Top-level clock for blocks running at system
107 (options
, args
) = parser
.parse_args()
110 print "Error: script doesn't take any positional arguments"
113 # Get the total number of testers
114 def numtesters(cachespec
, testerspec
):
115 # Determine the tester multiplier for each level as the
116 # elements are per subsystem and it fans out
119 multiplier
.append(multiplier
[-1] * c
)
122 for t
, m
in zip(testerspec
, multiplier
):
129 # Start by parsing the command line options and do some basic sanity
132 # Generate a tree with a valid number of testers
134 tree_depth
= random
.randint(1, 4)
135 cachespec
= [random
.randint(1, 3) for i
in range(tree_depth
)]
136 testerspec
= [random
.randint(1, 3) for i
in range(tree_depth
+ 1)]
137 if numtesters(cachespec
, testerspec
) < block_size
:
140 print "Generated random tree -c", ':'.join(map(str, cachespec
)), \
141 "-t", ':'.join(map(str, testerspec
))
144 cachespec
= [int(x
) for x
in options
.caches
.split(':')]
145 testerspec
= [int(x
) for x
in options
.testers
.split(':')]
147 print "Error: Unable to parse caches or testers option"
150 if len(cachespec
) < 1:
151 print "Error: Must have at least one level of caches"
154 if len(cachespec
) != len(testerspec
) - 1:
155 print "Error: Testers must have one element more than caches"
158 if testerspec
[-1] == 0:
159 print "Error: Must have testers at the uppermost level"
164 print "Error: Cannot have a negative number of testers"
169 print "Error: Must have 1 or more caches at each level"
172 if numtesters(cachespec
, testerspec
) > block_size
:
173 print "Error: Limited to %s testers because of false sharing" \
177 # Define a prototype L1 cache that we scale for all successive levels
178 proto_l1
= Cache(size
= '32kB', assoc
= 4,
179 hit_latency
= 1, response_latency
= 1,
180 tgts_per_mshr
= 8, clusivity
= 'mostly_incl',
181 writeback_clean
= True)
188 cache_proto
= [proto_l1
]
190 # Now add additional cache levels (if any) by scaling L1 params, the
191 # first element is Ln, and the last element L1
192 for scale
in cachespec
[:-1]:
193 # Clone previous level and update params
194 prev
= cache_proto
[0]
196 next
.size
= prev
.size
* scale
197 next
.hit_latency
= prev
.hit_latency
* 10
198 next
.response_latency
= prev
.response_latency
* 10
199 next
.assoc
= prev
.assoc
* scale
200 next
.mshrs
= prev
.mshrs
* scale
202 # Swap the inclusivity/exclusivity at each level. L2 is mostly
203 # exclusive with respect to L1, L3 mostly inclusive, L4 mostly
205 next
.writeback_clean
= not prev
.writeback_clean
206 if (prev
.clusivity
.value
== 'mostly_incl'):
207 next
.clusivity
= 'mostly_excl'
209 next
.clusivity
= 'mostly_incl'
211 cache_proto
.insert(0, next
)
213 # Make a prototype for the tester to be used throughout
214 proto_tester
= MemTest(max_loads
= options
.maxloads
,
215 percent_functional
= options
.functional
,
216 percent_uncacheable
= options
.uncacheable
,
217 progress_interval
= options
.progress
)
219 # Set up the system along with a simple memory and reference memory
220 system
= System(physmem
= SimpleMemory(),
221 cache_line_size
= block_size
)
223 system
.voltage_domain
= VoltageDomain(voltage
= '1V')
225 system
.clk_domain
= SrcClockDomain(clock
= options
.sys_clock
,
226 voltage_domain
= system
.voltage_domain
)
228 # For each level, track the next subsys index to use
229 next_subsys_index
= [0] * (len(cachespec
) + 1)
231 # Recursive function to create a sub-tree of the cache and tester
233 def make_cache_level(ncaches
, prototypes
, level
, next_cache
):
234 global next_subsys_index
, proto_l1
, testerspec
, proto_tester
236 index
= next_subsys_index
[level
]
237 next_subsys_index
[level
] += 1
239 # Create a subsystem to contain the crossbar and caches, and
242 setattr(system
, 'l%dsubsys%d' % (level
, index
), subsys
)
244 # The levels are indexing backwards through the list
245 ntesters
= testerspec
[len(cachespec
) - level
]
247 # Scale the progress threshold as testers higher up in the tree
248 # (smaller level) get a smaller portion of the overall bandwidth,
249 # and also make the interval of packet injection longer for the
250 # testers closer to the memory (larger level) to prevent them
251 # hogging all the bandwidth
252 limit
= (len(cachespec
) - level
+ 1) * 100000000
253 testers
= [proto_tester(interval
= 10 * (level
* level
+ 1),
254 progress_check
= limit
) \
255 for i
in xrange(ntesters
)]
257 subsys
.tester
= testers
260 # Create a crossbar and add it to the subsystem, note that
261 # we do this even with a single element on this level
265 xbar
.master
= next_cache
.cpu_side
267 # Create and connect the caches, both the ones fanning out
268 # to create the tree, and the ones used to connect testers
270 tree_caches
= [prototypes
[0]() for i
in xrange(ncaches
[0])]
271 tester_caches
= [proto_l1() for i
in xrange(ntesters
)]
273 subsys
.cache
= tester_caches
+ tree_caches
274 for cache
in tree_caches
:
275 cache
.mem_side
= xbar
.slave
276 make_cache_level(ncaches
[1:], prototypes
[1:], level
- 1, cache
)
277 for tester
, cache
in zip(testers
, tester_caches
):
278 tester
.port
= cache
.cpu_side
279 cache
.mem_side
= xbar
.slave
282 print "Error: No next-level cache at top level"
286 # Create a crossbar and add it to the subsystem
289 xbar
.master
= next_cache
.cpu_side
290 for tester
in testers
:
291 tester
.port
= xbar
.slave
294 testers
[0].port
= next_cache
.cpu_side
296 # Top level call to create the cache hierarchy, bottom up
297 make_cache_level(cachespec
, cache_proto
, len(cachespec
), None)
299 # Connect the lowest level crossbar to the memory
300 last_subsys
= getattr(system
, 'l%dsubsys0' % len(cachespec
))
301 last_subsys
.xbar
.master
= system
.physmem
.port
303 root
= Root(full_system
= False, system
= system
)
305 root
.system
.mem_mode
= 'atomic'
307 root
.system
.mem_mode
= 'timing'
309 # The system port is never used in the tester so merely connect it
311 root
.system
.system_port
= last_subsys
.xbar
.slave
313 # Instantiate configuration
316 # Simulate until program terminates
317 exit_event
= m5
.simulate(options
.maxtick
)
319 print 'Exiting @ tick', m5
.curTick(), 'because', exit_event
.getCause()