configs/example/memtest.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
   4 # Redistribution and use in source and binary forms, with or without
   5 # modification, are permitted provided that the following conditions are
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   7 # notice, this list of conditions and the following disclaimer;
   8 # redistributions in binary form must reproduce the above copyright
   9 # notice, this list of conditions and the following disclaimer in the
  10 # documentation and/or other materials provided with the distribution;
  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Ron Dreslinski
  28
  29 import optparse
  30 import sys
  31
  32 import m5
  33 from m5.objects import *
  34
  35 parser = optparse.OptionParser()
  36
  37 parser.add_option("-a", "--atomic", action="store_true",
  38                   help="Use atomic (non-timing) mode")
  39 parser.add_option("-b", "--blocking", action="store_true",
  40                   help="Use blocking caches")
  41 parser.add_option("-l", "--maxloads", metavar="N", default=0,
  42                   help="Stop after N loads")
  43 parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
  44                   metavar="T",
  45                   help="Stop after T ticks")
  46
  47 #
  48 # The "tree" specification is a colon-separated list of one or more
  49 # integers.  The first integer is the number of caches/testers
  50 # connected directly to main memory.  The last integer in the list is
  51 # the number of testers associated with the uppermost level of memory
  52 # (L1 cache, if there are caches, or main memory if no caches).  Thus
  53 # if there is only one integer, there are no caches, and the integer
  54 # specifies the number of testers connected directly to main memory.
  55 # The other integers (if any) specify the number of caches at each
  56 # level of the hierarchy between.
  57 #
  58 # Examples:
  59 #
  60 #  "2:1"    Two caches connected to memory with a single tester behind each
  61 #           (single-level hierarchy, two testers total)
  62 #
  63 #  "2:2:1"  Two-level hierarchy, 2 L1s behind each of 2 L2s, 4 testers total
  64 #
  65 parser.add_option("-t", "--treespec", type="string", default="8:1",
  66                   help="Colon-separated multilevel tree specification, "
  67                   "see script comments for details "
  68                   "[default: %default]")
  69
  70 parser.add_option("--force-bus", action="store_true",
  71                   help="Use bus between levels even with single cache")
  72
  73 parser.add_option("-f", "--functional", type="int", default=0,
  74                   metavar="PCT",
  75                   help="Target percentage of functional accesses "
  76                   "[default: %default]")
  77 parser.add_option("-u", "--uncacheable", type="int", default=0,
  78                   metavar="PCT",
  79                   help="Target percentage of uncacheable accesses "
  80                   "[default: %default]")
  81
  82 parser.add_option("--progress", type="int", default=1000,
  83                   metavar="NLOADS",
  84                   help="Progress message interval "
  85                   "[default: %default]")
  86 parser.add_option("--sys-clock", action="store", type="string",
  87                   default='1GHz',
  88                   help = """Top-level clock for blocks running at system
  89                   speed""")
  90
  91 (options, args) = parser.parse_args()
  92
  93 if args:
  94      print "Error: script doesn't take any positional arguments"
  95      sys.exit(1)
  96
  97 block_size = 64
  98
  99 try:
 100      treespec = [int(x) for x in options.treespec.split(':')]
 101      numtesters = reduce(lambda x,y: x*y, treespec)
 102 except:
 103      print "Error parsing treespec option"
 104      sys.exit(1)
 105
 106 if numtesters > block_size:
 107      print "Error: Number of testers limited to %s because of false sharing" \
 108            % (block_size)
 109      sys.exit(1)
 110
 111 if len(treespec) < 1:
 112      print "Error parsing treespec"
 113      sys.exit(1)
 114
 115 # define prototype L1 cache
 116 proto_l1 = BaseCache(size = '32kB', assoc = 4,
 117                      hit_latency = 1, response_latency = 1,
 118                      tgts_per_mshr = 8)
 119
 120 if options.blocking:
 121      proto_l1.mshrs = 1
 122 else:
 123      proto_l1.mshrs = 4
 124
 125 # build a list of prototypes, one for each level of treespec, starting
 126 # at the end (last entry is tester objects)
 127 prototypes = [ MemTest(atomic=options.atomic, max_loads=options.maxloads,
 128                        percent_functional=options.functional,
 129                        percent_uncacheable=options.uncacheable,
 130                        progress_interval=options.progress) ]
 131
 132 # next comes L1 cache, if any
 133 if len(treespec) > 1:
 134      prototypes.insert(0, proto_l1)
 135
 136 # now add additional cache levels (if any) by scaling L1 params
 137 for scale in treespec[:-2]:
 138      # clone previous level and update params
 139      prev = prototypes[0]
 140      next = prev()
 141      next.size = prev.size * scale
 142      next.hit_latency = prev.hit_latency * 10
 143      next.response_latency = prev.response_latency * 10
 144      next.assoc = prev.assoc * scale
 145      next.mshrs = prev.mshrs * scale
 146      prototypes.insert(0, next)
 147
 148 # system simulated
 149 system = System(funcmem = SimpleMemory(in_addr_map = False),
 150                 funcbus = NoncoherentXBar(),
 151                 physmem = SimpleMemory(latency = "100ns"),
 152                 cache_line_size = block_size)
 153
 154
 155 system.voltage_domain = VoltageDomain(voltage = '1V')
 156
 157 system.clk_domain = SrcClockDomain(clock =  options.sys_clock,
 158                         voltage_domain = system.voltage_domain)
 159
 160 def make_level(spec, prototypes, attach_obj, attach_port):
 161      fanout = spec[0]
 162      parent = attach_obj # use attach obj as config parent too
 163      if len(spec) > 1 and (fanout > 1 or options.force_bus):
 164           port = getattr(attach_obj, attach_port)
 165           new_bus = CoherentXBar(width=16)
 166           if (port.role == 'MASTER'):
 167                new_bus.slave = port
 168                attach_port = "master"
 169           else:
 170                new_bus.master = port
 171                attach_port = "slave"
 172           parent.cpu_side_bus = new_bus
 173           attach_obj = new_bus
 174      objs = [prototypes[0]() for i in xrange(fanout)]
 175      if len(spec) > 1:
 176           # we just built caches, more levels to go
 177           parent.cache = objs
 178           for cache in objs:
 179                cache.mem_side = getattr(attach_obj, attach_port)
 180                make_level(spec[1:], prototypes[1:], cache, "cpu_side")
 181      else:
 182           # we just built the MemTest objects
 183           parent.cpu = objs
 184           for t in objs:
 185                t.test = getattr(attach_obj, attach_port)
 186                t.functional = system.funcbus.slave
 187
 188 make_level(treespec, prototypes, system.physmem, "port")
 189
 190 # connect reference memory to funcbus
 191 system.funcbus.master = system.funcmem.port
 192
 193 # -----------------------
 194 # run simulation
 195 # -----------------------
 196
 197 root = Root( full_system = False, system = system )
 198 if options.atomic:
 199     root.system.mem_mode = 'atomic'
 200 else:
 201     root.system.mem_mode = 'timing'
 202
 203 # The system port is never used in the tester so merely connect it
 204 # to avoid problems
 205 root.system.system_port = root.system.funcbus.slave
 206
 207 # Not much point in this being higher than the L1 latency
 208 m5.ticks.setGlobalFrequency('1ns')
 209
 210 # instantiate configuration
 211 m5.instantiate()
 212
 213 # simulate until program terminates
 214 exit_event = m5.simulate(options.maxtick)
 215
 216 print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()