configs/example/memtest.py

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  38
  39 from __future__ import print_function
  40 from __future__ import absolute_import
  41
  42 import optparse
  43 import random
  44 import sys
  45
  46 import m5
  47 from m5.objects import *
  48
  49 # This example script stress tests the memory system by creating false
  50 # sharing in a tree topology. At the bottom of the tree is a shared
  51 # memory, and then at each level a number of testers are attached,
  52 # along with a number of caches that them selves fan out to subtrees
  53 # of testers and caches. Thus, it is possible to create a system with
  54 # arbitrarily deep cache hierarchies, sharing or no sharing of caches,
  55 # and testers not only at the L1s, but also at the L2s, L3s etc.
  56
  57 parser = optparse.OptionParser()
  58
  59 parser.add_option("-a", "--atomic", action="store_true",
  60                   help="Use atomic (non-timing) mode")
  61 parser.add_option("-b", "--blocking", action="store_true",
  62                   help="Use blocking caches")
  63 parser.add_option("-l", "--maxloads", metavar="N", default=0,
  64                   help="Stop after N loads")
  65 parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
  66                   metavar="T",
  67                   help="Stop after T ticks")
  68
  69 # The tree specification consists of two colon-separated lists of one
  70 # or more integers, one for the caches, and one for the testers. The
  71 # first integer is the number of caches/testers closest to main
  72 # memory. Each cache then fans out to a subtree. The last integer in
  73 # the list is the number of caches/testers associated with the
  74 # uppermost level of memory. The other integers (if any) specify the
  75 # number of caches/testers connected at each level of the crossbar
  76 # hierarchy. The tester string should have one element more than the
  77 # cache string as there should always be testers attached to the
  78 # uppermost caches.
  79
  80 parser.add_option("-c", "--caches", type="string", default="2:2:1",
  81                   help="Colon-separated cache hierarchy specification, "
  82                   "see script comments for details "
  83                   "[default: %default]")
  84 parser.add_option("--noncoherent-cache", action="store_true",
  85                   help="Adds a non-coherent, last-level cache")
  86 parser.add_option("-t", "--testers", type="string", default="1:1:0:2",
  87                   help="Colon-separated tester hierarchy specification, "
  88                   "see script comments for details "
  89                   "[default: %default]")
  90 parser.add_option("-f", "--functional", type="int", default=10,
  91                   metavar="PCT",
  92                   help="Target percentage of functional accesses "
  93                   "[default: %default]")
  94 parser.add_option("-u", "--uncacheable", type="int", default=10,
  95                   metavar="PCT",
  96                   help="Target percentage of uncacheable accesses "
  97                   "[default: %default]")
  98 parser.add_option("-r", "--random", action="store_true",
  99                   help="Generate a random tree topology")
 100 parser.add_option("--progress", type="int", default=100000,
 101                   metavar="NLOADS",
 102                   help="Progress message interval "
 103                   "[default: %default]")
 104 parser.add_option("--sys-clock", action="store", type="string",
 105                   default='1GHz',
 106                   help = """Top-level clock for blocks running at system
 107                   speed""")
 108
 109 (options, args) = parser.parse_args()
 110
 111 if args:
 112      print("Error: script doesn't take any positional arguments")
 113      sys.exit(1)
 114
 115 # Get the total number of testers
 116 def numtesters(cachespec, testerspec):
 117      # Determine the tester multiplier for each level as the
 118      # elements are per subsystem and it fans out
 119      multiplier = [1]
 120      for c in cachespec:
 121           multiplier.append(multiplier[-1] * c)
 122
 123      total = 0
 124      for t, m in zip(testerspec, multiplier):
 125           total += t * m
 126
 127      return total
 128
 129 block_size = 64
 130
 131 # Start by parsing the command line options and do some basic sanity
 132 # checking
 133 if options.random:
 134      # Generate a tree with a valid number of testers
 135      while True:
 136           tree_depth = random.randint(1, 4)
 137           cachespec = [random.randint(1, 3) for i in range(tree_depth)]
 138           testerspec = [random.randint(1, 3) for i in range(tree_depth + 1)]
 139           if numtesters(cachespec, testerspec) < block_size:
 140                break
 141
 142      print("Generated random tree -c", ':'.join(map(str, cachespec)),
 143          "-t", ':'.join(map(str, testerspec)))
 144 else:
 145      try:
 146           cachespec = [int(x) for x in options.caches.split(':')]
 147           testerspec = [int(x) for x in options.testers.split(':')]
 148      except:
 149           print("Error: Unable to parse caches or testers option")
 150           sys.exit(1)
 151
 152      if len(cachespec) < 1:
 153           print("Error: Must have at least one level of caches")
 154           sys.exit(1)
 155
 156      if len(cachespec) != len(testerspec) - 1:
 157           print("Error: Testers must have one element more than caches")
 158           sys.exit(1)
 159
 160      if testerspec[-1] == 0:
 161           print("Error: Must have testers at the uppermost level")
 162           sys.exit(1)
 163
 164      for t in testerspec:
 165           if t < 0:
 166                print("Error: Cannot have a negative number of testers")
 167                sys.exit(1)
 168
 169      for c in cachespec:
 170           if c < 1:
 171                print("Error: Must have 1 or more caches at each level")
 172                sys.exit(1)
 173
 174      if numtesters(cachespec, testerspec) > block_size:
 175           print("Error: Limited to %s testers because of false sharing"
 176               % (block_size))
 177           sys.exit(1)
 178
 179 # Define a prototype L1 cache that we scale for all successive levels
 180 proto_l1 = Cache(size = '32kB', assoc = 4,
 181                  tag_latency = 1, data_latency = 1, response_latency = 1,
 182                  tgts_per_mshr = 8, clusivity = 'mostly_incl',
 183                  writeback_clean = True)
 184
 185 if options.blocking:
 186      proto_l1.mshrs = 1
 187 else:
 188      proto_l1.mshrs = 4
 189
 190 cache_proto = [proto_l1]
 191
 192 # Now add additional cache levels (if any) by scaling L1 params, the
 193 # first element is Ln, and the last element L1
 194 for scale in cachespec[:-1]:
 195      # Clone previous level and update params
 196      prev = cache_proto[0]
 197      next = prev()
 198      next.size = prev.size * scale
 199      next.tag_latency = prev.tag_latency * 10
 200      next.data_latency = prev.data_latency * 10
 201      next.response_latency = prev.response_latency * 10
 202      next.assoc = prev.assoc * scale
 203      next.mshrs = prev.mshrs * scale
 204
 205      # Swap the inclusivity/exclusivity at each level. L2 is mostly
 206      # exclusive with respect to L1, L3 mostly inclusive, L4 mostly
 207      # exclusive etc.
 208      next.writeback_clean = not prev.writeback_clean
 209      if (prev.clusivity.value == 'mostly_incl'):
 210           next.clusivity = 'mostly_excl'
 211      else:
 212           next.clusivity = 'mostly_incl'
 213
 214      cache_proto.insert(0, next)
 215
 216 # Make a prototype for the tester to be used throughout
 217 proto_tester = MemTest(max_loads = options.maxloads,
 218                        percent_functional = options.functional,
 219                        percent_uncacheable = options.uncacheable,
 220                        progress_interval = options.progress)
 221
 222 # Set up the system along with a simple memory and reference memory
 223 system = System(physmem = SimpleMemory(),
 224                 cache_line_size = block_size)
 225
 226 system.voltage_domain = VoltageDomain(voltage = '1V')
 227
 228 system.clk_domain = SrcClockDomain(clock =  options.sys_clock,
 229                         voltage_domain = system.voltage_domain)
 230
 231 # For each level, track the next subsys index to use
 232 next_subsys_index = [0] * (len(cachespec) + 1)
 233
 234 # Recursive function to create a sub-tree of the cache and tester
 235 # hierarchy
 236 def make_cache_level(ncaches, prototypes, level, next_cache):
 237      global next_subsys_index, proto_l1, testerspec, proto_tester
 238
 239      index = next_subsys_index[level]
 240      next_subsys_index[level] += 1
 241
 242      # Create a subsystem to contain the crossbar and caches, and
 243      # any testers
 244      subsys = SubSystem()
 245      setattr(system, 'l%dsubsys%d' % (level, index), subsys)
 246
 247      # The levels are indexing backwards through the list
 248      ntesters = testerspec[len(cachespec) - level]
 249
 250      # Scale the progress threshold as testers higher up in the tree
 251      # (smaller level) get a smaller portion of the overall bandwidth,
 252      # and also make the interval of packet injection longer for the
 253      # testers closer to the memory (larger level) to prevent them
 254      # hogging all the bandwidth
 255      limit = (len(cachespec) - level + 1) * 100000000
 256      testers = [proto_tester(interval = 10 * (level * level + 1),
 257                              progress_check = limit) \
 258                      for i in range(ntesters)]
 259      if ntesters:
 260           subsys.tester = testers
 261
 262      if level != 0:
 263           # Create a crossbar and add it to the subsystem, note that
 264           # we do this even with a single element on this level
 265           xbar = L2XBar()
 266           subsys.xbar = xbar
 267           if next_cache:
 268                xbar.master = next_cache.cpu_side
 269
 270           # Create and connect the caches, both the ones fanning out
 271           # to create the tree, and the ones used to connect testers
 272           # on this level
 273           tree_caches = [prototypes[0]() for i in range(ncaches[0])]
 274           tester_caches = [proto_l1() for i in range(ntesters)]
 275
 276           subsys.cache = tester_caches + tree_caches
 277           for cache in tree_caches:
 278                cache.mem_side = xbar.slave
 279                make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache)
 280           for tester, cache in zip(testers, tester_caches):
 281                tester.port = cache.cpu_side
 282                cache.mem_side = xbar.slave
 283      else:
 284           if not next_cache:
 285                print("Error: No next-level cache at top level")
 286                sys.exit(1)
 287
 288           if ntesters > 1:
 289                # Create a crossbar and add it to the subsystem
 290                xbar = L2XBar()
 291                subsys.xbar = xbar
 292                xbar.master = next_cache.cpu_side
 293                for tester in testers:
 294                     tester.port = xbar.slave
 295           else:
 296                # Single tester
 297                testers[0].port = next_cache.cpu_side
 298
 299 # Top level call to create the cache hierarchy, bottom up
 300 make_cache_level(cachespec, cache_proto, len(cachespec), None)
 301
 302 # Connect the lowest level crossbar to the last-level cache and memory
 303 # controller
 304 last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec))
 305 last_subsys.xbar.point_of_coherency = True
 306 if options.noncoherent_cache:
 307      system.llc = NoncoherentCache(size = '16MB', assoc = 16, tag_latency = 10,
 308                                    data_latency = 10, sequential_access = True,
 309                                    response_latency = 20, tgts_per_mshr = 8,
 310                                    mshrs = 64)
 311      last_subsys.xbar.master = system.llc.cpu_side
 312      system.llc.mem_side = system.physmem.port
 313 else:
 314      last_subsys.xbar.master = system.physmem.port
 315
 316 root = Root(full_system = False, system = system)
 317 if options.atomic:
 318     root.system.mem_mode = 'atomic'
 319 else:
 320     root.system.mem_mode = 'timing'
 321
 322 # The system port is never used in the tester so merely connect it
 323 # to avoid problems
 324 root.system.system_port = last_subsys.xbar.slave
 325
 326 # Instantiate configuration
 327 m5.instantiate()
 328
 329 # Simulate until program terminates
 330 exit_event = m5.simulate(options.maxtick)
 331
 332 print('Exiting @ tick', m5.curTick(), 'because', exit_event.getCause())