configs/example/memtest.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
   4 # Redistribution and use in source and binary forms, with or without
   5 # modification, are permitted provided that the following conditions are
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   7 # notice, this list of conditions and the following disclaimer;
   8 # redistributions in binary form must reproduce the above copyright
   9 # notice, this list of conditions and the following disclaimer in the
  10 # documentation and/or other materials provided with the distribution;
  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Ron Dreslinski
  28
  29 import optparse
  30 import sys
  31
  32 import m5
  33 from m5.objects import *
  34
  35 parser = optparse.OptionParser()
  36
  37 parser.add_option("-a", "--atomic", action="store_true",
  38                   help="Use atomic (non-timing) mode")
  39 parser.add_option("-b", "--blocking", action="store_true",
  40                   help="Use blocking caches")
  41 parser.add_option("-l", "--maxloads", metavar="N", default=0,
  42                   help="Stop after N loads")
  43 parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
  44                   metavar="T",
  45                   help="Stop after T ticks")
  46
  47 #
  48 # The "tree" specification is a colon-separated list of one or more
  49 # integers.  The first integer is the number of caches/testers
  50 # connected directly to main memory.  The last integer in the list is
  51 # the number of testers associated with the uppermost level of memory
  52 # (L1 cache, if there are caches, or main memory if no caches).  Thus
  53 # if there is only one integer, there are no caches, and the integer
  54 # specifies the number of testers connected directly to main memory.
  55 # The other integers (if any) specify the number of caches at each
  56 # level of the hierarchy between.
  57 #
  58 # Examples:
  59 #
  60 #  "2:1"    Two caches connected to memory with a single tester behind each
  61 #           (single-level hierarchy, two testers total)
  62 #
  63 #  "2:2:1"  Two-level hierarchy, 2 L1s behind each of 2 L2s, 4 testers total
  64 #
  65 parser.add_option("-t", "--treespec", type="string", default="8:1",
  66                   help="Colon-separated multilevel tree specification, "
  67                   "see script comments for details "
  68                   "[default: %default]")
  69
  70 parser.add_option("--force-bus", action="store_true",
  71                   help="Use bus between levels even with single cache")
  72
  73 parser.add_option("-f", "--functional", type="int", default=0,
  74                   metavar="PCT",
  75                   help="Target percentage of functional accesses "
  76                   "[default: %default]")
  77 parser.add_option("-u", "--uncacheable", type="int", default=0,
  78                   metavar="PCT",
  79                   help="Target percentage of uncacheable accesses "
  80                   "[default: %default]")
  81
  82 parser.add_option("--progress", type="int", default=1000,
  83                   metavar="NLOADS",
  84                   help="Progress message interval "
  85                   "[default: %default]")
  86
  87 (options, args) = parser.parse_args()
  88
  89 if args:
  90      print "Error: script doesn't take any positional arguments"
  91      sys.exit(1)
  92
  93 block_size = 64
  94
  95 try:
  96      treespec = [int(x) for x in options.treespec.split(':')]
  97      numtesters = reduce(lambda x,y: x*y, treespec)
  98 except:
  99      print "Error parsing treespec option"
 100      sys.exit(1)
 101
 102 if numtesters > block_size:
 103      print "Error: Number of testers limited to %s because of false sharing" \
 104            % (block_size)
 105      sys.exit(1)
 106
 107 if len(treespec) < 1:
 108      print "Error parsing treespec"
 109      sys.exit(1)
 110
 111 # define prototype L1 cache
 112 proto_l1 = BaseCache(size = '32kB', assoc = 4, block_size = block_size,
 113                      latency = '1ns', tgts_per_mshr = 8)
 114
 115 if options.blocking:
 116      proto_l1.mshrs = 1
 117 else:
 118      proto_l1.mshrs = 8
 119
 120 # build a list of prototypes, one for each level of treespec, starting
 121 # at the end (last entry is tester objects)
 122 prototypes = [ MemTest(atomic=options.atomic, max_loads=options.maxloads,
 123                        percent_functional=options.functional,
 124                        percent_uncacheable=options.uncacheable,
 125                        progress_interval=options.progress) ]
 126
 127 # next comes L1 cache, if any
 128 if len(treespec) > 1:
 129      prototypes.insert(0, proto_l1)
 130
 131 # now add additional cache levels (if any) by scaling L1 params
 132 while len(prototypes) < len(treespec):
 133      # clone previous level and update params
 134      prev = prototypes[0]
 135      next = prev()
 136      next.size = prev.size * 4
 137      next.latency = prev.latency * 10
 138      next.assoc = prev.assoc * 2
 139      prototypes.insert(0, next)
 140
 141 # system simulated
 142 system = System(funcmem = PhysicalMemory(),
 143                 physmem = PhysicalMemory(latency = "100ns"))
 144
 145 def make_level(spec, prototypes, attach_obj, attach_port):
 146      fanout = spec[0]
 147      parent = attach_obj # use attach obj as config parent too
 148      if len(spec) > 1 and (fanout > 1 or options.force_bus):
 149           new_bus = Bus(clock="500MHz", width=16)
 150           new_bus.port = getattr(attach_obj, attach_port)
 151           parent.cpu_side_bus = new_bus
 152           attach_obj = new_bus
 153           attach_port = "port"
 154      objs = [prototypes[0]() for i in xrange(fanout)]
 155      if len(spec) > 1:
 156           # we just built caches, more levels to go
 157           parent.cache = objs
 158           for cache in objs:
 159                cache.mem_side = getattr(attach_obj, attach_port)
 160                make_level(spec[1:], prototypes[1:], cache, "cpu_side")
 161      else:
 162           # we just built the MemTest objects
 163           parent.cpu = objs
 164           for t in objs:
 165                t.test = getattr(attach_obj, attach_port)
 166                t.functional = system.funcmem.port
 167
 168 make_level(treespec, prototypes, system.physmem, "port")
 169
 170 # -----------------------
 171 # run simulation
 172 # -----------------------
 173
 174 root = Root( system = system )
 175 if options.atomic:
 176     root.system.mem_mode = 'atomic'
 177 else:
 178     root.system.mem_mode = 'timing'
 179
 180 # Not much point in this being higher than the L1 latency
 181 m5.ticks.setGlobalFrequency('1ns')
 182
 183 # instantiate configuration
 184 m5.instantiate()
 185
 186 # simulate until program terminates
 187 exit_event = m5.simulate(options.maxtick)
 188
 189 print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()