configs/example/memtest.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
   4 # Redistribution and use in source and binary forms, with or without
   5 # modification, are permitted provided that the following conditions are
   6 # met: redistributions of source code must retain the above copyright
   7 # notice, this list of conditions and the following disclaimer;
   8 # redistributions in binary form must reproduce the above copyright
   9 # notice, this list of conditions and the following disclaimer in the
  10 # documentation and/or other materials provided with the distribution;
  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Ron Dreslinski
  28
  29 import m5
  30 from m5.objects import *
  31 import os, optparse, sys
  32 m5.AddToPath('../common')
  33
  34 parser = optparse.OptionParser()
  35
  36 parser.add_option("-c", "--cache-levels", type="int", default=2,
  37                   metavar="LEVELS",
  38                   help="Number of cache levels [default: %default]")
  39 parser.add_option("-a", "--atomic", action="store_true",
  40                   help="Use atomic (non-timing) mode")
  41 parser.add_option("-b", "--blocking", action="store_true",
  42                   help="Use blocking caches")
  43 parser.add_option("-l", "--maxloads", default="1G", metavar="N",
  44                   help="Stop after N loads [default: %default]")
  45 parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
  46                   metavar="T",
  47                   help="Stop after T ticks")
  48 parser.add_option("-n", "--numtesters", type="int", default=8,
  49                   metavar="N",
  50                   help="Number of tester pseudo-CPUs [default: %default]")
  51 parser.add_option("-p", "--protocol", default="moesi",
  52                   help="Coherence protocol [default: %default]")
  53
  54 parser.add_option("-f", "--functional", type="int", default=0,
  55                   metavar="PCT",
  56                   help="Target percentage of functional accesses "
  57                   "[default: %default]")
  58 parser.add_option("-u", "--uncacheable", type="int", default=0,
  59                   metavar="PCT",
  60                   help="Target percentage of uncacheable accesses "
  61                   "[default: %default]")
  62
  63 parser.add_option("--progress", type="int", default=1000,
  64                   metavar="NLOADS",
  65                   help="Progress message interval "
  66                   "[default: %default]")
  67
  68 (options, args) = parser.parse_args()
  69
  70 if args:
  71      print "Error: script doesn't take any positional arguments"
  72      sys.exit(1)
  73
  74 # Should generalize this someday... would be cool to have a loop that
  75 # just iterates, adding a level of caching each time.
  76 #if options.cache_levels != 2 and options.cache_levels != 0:
  77 #     print "Error: number of cache levels must be 0 or 2"
  78 #     sys.exit(1)
  79
  80 if options.blocking:
  81      num_l1_mshrs = 1
  82      num_l2_mshrs = 1
  83 else:
  84      num_l1_mshrs = 12
  85      num_l2_mshrs = 92
  86
  87 block_size = 64
  88
  89 # --------------------
  90 # Base L1 Cache
  91 # ====================
  92
  93 class L1(BaseCache):
  94     latency = '1ns'
  95     block_size = block_size
  96     mshrs = num_l1_mshrs
  97     tgts_per_mshr = 8
  98     protocol = CoherenceProtocol(protocol=options.protocol)
  99
 100 # ----------------------
 101 # Base L2 Cache
 102 # ----------------------
 103
 104 class L2(BaseCache):
 105     block_size = block_size
 106     latency = '10ns'
 107     mshrs = num_l2_mshrs
 108     tgts_per_mshr = 16
 109     write_buffers = 8
 110     protocol = CoherenceProtocol(protocol=options.protocol)
 111
 112 if options.numtesters > block_size:
 113      print "Error: Number of testers limited to %s because of false sharing" \
 114            % (block_size)
 115      sys.exit(1)
 116
 117 cpus = [ MemTest(atomic=options.atomic, max_loads=options.maxloads,
 118                  percent_functional=options.functional,
 119                  percent_uncacheable=options.uncacheable,
 120                  progress_interval=options.progress)
 121          for i in xrange(options.numtesters) ]
 122
 123 # system simulated
 124 system = System(cpu = cpus, funcmem = PhysicalMemory(),
 125                 physmem = PhysicalMemory(latency = "100ns"),
 126                 membus = Bus(clock="500MHz", width=16))
 127
 128 # l2cache & bus
 129 if options.cache_levels == 2:
 130     system.toL2Bus = Bus(clock="500MHz", width=16)
 131     system.l2c = L2(size='64kB', assoc=8)
 132     system.l2c.cpu_side = system.toL2Bus.port
 133
 134     # connect l2c to membus
 135     system.l2c.mem_side = system.membus.port
 136
 137 # add L1 caches
 138 for cpu in cpus:
 139     if options.cache_levels == 2:
 140          cpu.l1c = L1(size = '32kB', assoc = 4)
 141          cpu.test = cpu.l1c.cpu_side
 142          cpu.l1c.mem_side = system.toL2Bus.port
 143     elif options.cache_levels == 1:
 144          cpu.l1c = L1(size = '32kB', assoc = 4)
 145          cpu.test = cpu.l1c.cpu_side
 146          cpu.l1c.mem_side = system.membus.port
 147     else:
 148          cpu.test = system.membus.port
 149     system.funcmem.port = cpu.functional
 150
 151 # connect memory to membus
 152 system.physmem.port = system.membus.port
 153
 154
 155 # -----------------------
 156 # run simulation
 157 # -----------------------
 158
 159 root = Root( system = system )
 160 if options.atomic:
 161     root.system.mem_mode = 'atomic'
 162 else:
 163     root.system.mem_mode = 'timing'
 164
 165 # Not much point in this being higher than the L1 latency
 166 m5.ticks.setGlobalFrequency('1ns')
 167
 168 # instantiate configuration
 169 m5.instantiate(root)
 170
 171 # simulate until program terminates
 172 exit_event = m5.simulate(options.maxtick)
 173
 174 print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()