1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
6 # met: redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer;
8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution;
11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 # Authors: Ron Dreslinski
33 from m5
.objects
import *
35 parser
= optparse
.OptionParser()
37 parser
.add_option("-a", "--atomic", action
="store_true",
38 help="Use atomic (non-timing) mode")
39 parser
.add_option("-b", "--blocking", action
="store_true",
40 help="Use blocking caches")
41 parser
.add_option("-l", "--maxloads", metavar
="N", default
=0,
42 help="Stop after N loads")
43 parser
.add_option("-m", "--maxtick", type="int", default
=m5
.MaxTick
,
45 help="Stop after T ticks")
48 # The "tree" specification is a colon-separated list of one or more
49 # integers. The first integer is the number of caches/testers
50 # connected directly to main memory. The last integer in the list is
51 # the number of testers associated with the uppermost level of memory
52 # (L1 cache, if there are caches, or main memory if no caches). Thus
53 # if there is only one integer, there are no caches, and the integer
54 # specifies the number of testers connected directly to main memory.
55 # The other integers (if any) specify the number of caches at each
56 # level of the hierarchy between.
60 # "2:1" Two caches connected to memory with a single tester behind each
61 # (single-level hierarchy, two testers total)
63 # "2:2:1" Two-level hierarchy, 2 L1s behind each of 2 L2s, 4 testers total
65 parser
.add_option("-t", "--treespec", type="string", default
="8:1",
66 help="Colon-separated multilevel tree specification, "
67 "see script comments for details "
68 "[default: %default]")
70 parser
.add_option("--force-bus", action
="store_true",
71 help="Use bus between levels even with single cache")
73 parser
.add_option("-f", "--functional", type="int", default
=0,
75 help="Target percentage of functional accesses "
76 "[default: %default]")
77 parser
.add_option("-u", "--uncacheable", type="int", default
=0,
79 help="Target percentage of uncacheable accesses "
80 "[default: %default]")
82 parser
.add_option("--progress", type="int", default
=1000,
84 help="Progress message interval "
85 "[default: %default]")
87 (options
, args
) = parser
.parse_args()
90 print "Error: script doesn't take any positional arguments"
96 treespec
= [int(x
) for x
in options
.treespec
.split(':')]
97 numtesters
= reduce(lambda x
,y
: x
*y
, treespec
)
99 print "Error parsing treespec option"
102 if numtesters
> block_size
:
103 print "Error: Number of testers limited to %s because of false sharing" \
107 if len(treespec
) < 1:
108 print "Error parsing treespec"
111 # define prototype L1 cache
112 proto_l1
= BaseCache(size
= '32kB', assoc
= 4, block_size
= block_size
,
113 hit_latency
= '1ns', response_latency
= '1ns',
121 # build a list of prototypes, one for each level of treespec, starting
122 # at the end (last entry is tester objects)
123 prototypes
= [ MemTest(atomic
=options
.atomic
, max_loads
=options
.maxloads
,
124 percent_functional
=options
.functional
,
125 percent_uncacheable
=options
.uncacheable
,
126 progress_interval
=options
.progress
) ]
128 # next comes L1 cache, if any
129 if len(treespec
) > 1:
130 prototypes
.insert(0, proto_l1
)
132 # now add additional cache levels (if any) by scaling L1 params
133 for scale
in treespec
[:-2]:
134 # clone previous level and update params
137 next
.size
= prev
.size
* scale
138 next
.latency
= prev
.latency
* 10
139 next
.assoc
= prev
.assoc
* scale
140 next
.mshrs
= prev
.mshrs
* scale
141 prototypes
.insert(0, next
)
144 system
= System(funcmem
= SimpleMemory(in_addr_map
= False),
145 funcbus
= NoncoherentBus(),
146 physmem
= SimpleMemory(latency
= "100ns"))
147 system
.clk_domain
= SrcClockDomain(clock
= options
.sys_clock
)
149 def make_level(spec
, prototypes
, attach_obj
, attach_port
):
151 parent
= attach_obj
# use attach obj as config parent too
152 if len(spec
) > 1 and (fanout
> 1 or options
.force_bus
):
153 port
= getattr(attach_obj
, attach_port
)
154 new_bus
= CoherentBus(width
=16)
155 if (port
.role
== 'MASTER'):
157 attach_port
= "master"
159 new_bus
.master
= port
160 attach_port
= "slave"
161 parent
.cpu_side_bus
= new_bus
163 objs
= [prototypes
[0]() for i
in xrange(fanout
)]
165 # we just built caches, more levels to go
168 cache
.mem_side
= getattr(attach_obj
, attach_port
)
169 make_level(spec
[1:], prototypes
[1:], cache
, "cpu_side")
171 # we just built the MemTest objects
174 t
.test
= getattr(attach_obj
, attach_port
)
175 t
.functional
= system
.funcbus
.slave
177 make_level(treespec
, prototypes
, system
.physmem
, "port")
179 # connect reference memory to funcbus
180 system
.funcbus
.master
= system
.funcmem
.port
182 # -----------------------
184 # -----------------------
186 root
= Root( full_system
= False, system
= system
)
188 root
.system
.mem_mode
= 'atomic'
190 root
.system
.mem_mode
= 'timing'
192 # The system port is never used in the tester so merely connect it
194 root
.system
.system_port
= root
.system
.funcbus
.slave
196 # Not much point in this being higher than the L1 latency
197 m5
.ticks
.setGlobalFrequency('1ns')
199 # instantiate configuration
202 # simulate until program terminates
203 exit_event
= m5
.simulate(options
.maxtick
)
205 print 'Exiting @ tick', m5
.curTick(), 'because', exit_event
.getCause()