configs/example/memtest.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
   4 # Redistribution and use in source and binary forms, with or without
   5 # modification, are permitted provided that the following conditions are
   6 # met: redistributions of source code must retain the above copyright
   7 # notice, this list of conditions and the following disclaimer;
   8 # redistributions in binary form must reproduce the above copyright
   9 # notice, this list of conditions and the following disclaimer in the
  10 # documentation and/or other materials provided with the distribution;
  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Ron Dreslinski
  28
  29 import m5
  30 from m5.objects import *
  31 import os, optparse, sys
  32 m5.AddToPath('../common')
  33
  34 parser = optparse.OptionParser()
  35
  36 parser.add_option("-c", "--cache-levels", type="int", default=2,
  37                   metavar="LEVELS",
  38                   help="Number of cache levels [default: %default]")
  39 parser.add_option("-a", "--atomic", action="store_true",
  40                   help="Use atomic (non-timing) mode")
  41 parser.add_option("-b", "--blocking", action="store_true",
  42                   help="Use blocking caches")
  43 parser.add_option("-l", "--maxloads", default="1G", metavar="N",
  44                   help="Stop after N loads [default: %default]")
  45 parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
  46                   metavar="T",
  47                   help="Stop after T ticks")
  48 parser.add_option("-n", "--numtesters", type="int", default=8,
  49                   metavar="N",
  50                   help="Number of tester pseudo-CPUs [default: %default]")
  51
  52 parser.add_option("-f", "--functional", type="int", default=0,
  53                   metavar="PCT",
  54                   help="Target percentage of functional accesses "
  55                   "[default: %default]")
  56 parser.add_option("-u", "--uncacheable", type="int", default=0,
  57                   metavar="PCT",
  58                   help="Target percentage of uncacheable accesses "
  59                   "[default: %default]")
  60
  61 parser.add_option("--progress", type="int", default=1000,
  62                   metavar="NLOADS",
  63                   help="Progress message interval "
  64                   "[default: %default]")
  65
  66 (options, args) = parser.parse_args()
  67
  68 if args:
  69      print "Error: script doesn't take any positional arguments"
  70      sys.exit(1)
  71
  72 # Should generalize this someday... would be cool to have a loop that
  73 # just iterates, adding a level of caching each time.
  74 #if options.cache_levels != 2 and options.cache_levels != 0:
  75 #     print "Error: number of cache levels must be 0 or 2"
  76 #     sys.exit(1)
  77
  78 if options.blocking:
  79      num_l1_mshrs = 1
  80      num_l2_mshrs = 1
  81 else:
  82      num_l1_mshrs = 12
  83      num_l2_mshrs = 92
  84
  85 block_size = 64
  86
  87 # --------------------
  88 # Base L1 Cache
  89 # ====================
  90
  91 class L1(BaseCache):
  92     latency = '1ns'
  93     block_size = block_size
  94     mshrs = num_l1_mshrs
  95     tgts_per_mshr = 8
  96
  97 # ----------------------
  98 # Base L2 Cache
  99 # ----------------------
 100
 101 class L2(BaseCache):
 102     block_size = block_size
 103     latency = '10ns'
 104     mshrs = num_l2_mshrs
 105     tgts_per_mshr = 16
 106     write_buffers = 8
 107
 108 if options.numtesters > block_size:
 109      print "Error: Number of testers limited to %s because of false sharing" \
 110            % (block_size)
 111      sys.exit(1)
 112
 113 cpus = [ MemTest(atomic=options.atomic, max_loads=options.maxloads,
 114                  percent_functional=options.functional,
 115                  percent_uncacheable=options.uncacheable,
 116                  progress_interval=options.progress)
 117          for i in xrange(options.numtesters) ]
 118
 119 # system simulated
 120 system = System(cpu = cpus, funcmem = PhysicalMemory(),
 121                 physmem = PhysicalMemory(latency = "100ns"),
 122                 membus = Bus(clock="500MHz", width=16))
 123
 124 # l2cache & bus
 125 if options.cache_levels == 2:
 126     system.toL2Bus = Bus(clock="500MHz", width=16)
 127     system.l2c = L2(size='64kB', assoc=8)
 128     system.l2c.cpu_side = system.toL2Bus.port
 129
 130     # connect l2c to membus
 131     system.l2c.mem_side = system.membus.port
 132
 133 # add L1 caches
 134 for cpu in cpus:
 135     if options.cache_levels == 2:
 136          cpu.l1c = L1(size = '32kB', assoc = 4)
 137          cpu.test = cpu.l1c.cpu_side
 138          cpu.l1c.mem_side = system.toL2Bus.port
 139     elif options.cache_levels == 1:
 140          cpu.l1c = L1(size = '32kB', assoc = 4)
 141          cpu.test = cpu.l1c.cpu_side
 142          cpu.l1c.mem_side = system.membus.port
 143     else:
 144          cpu.test = system.membus.port
 145     system.funcmem.port = cpu.functional
 146
 147 # connect memory to membus
 148 system.physmem.port = system.membus.port
 149
 150
 151 # -----------------------
 152 # run simulation
 153 # -----------------------
 154
 155 root = Root( system = system )
 156 if options.atomic:
 157     root.system.mem_mode = 'atomic'
 158 else:
 159     root.system.mem_mode = 'timing'
 160
 161 # Not much point in this being higher than the L1 latency
 162 m5.ticks.setGlobalFrequency('1ns')
 163
 164 # instantiate configuration
 165 m5.instantiate(root)
 166
 167 # simulate until program terminates
 168 exit_event = m5.simulate(options.maxtick)
 169
 170 print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()