configs/example/memtest.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
   4 # Redistribution and use in source and binary forms, with or without
   5 # modification, are permitted provided that the following conditions are
   6 # met: redistributions of source code must retain the above copyright
   7 # notice, this list of conditions and the following disclaimer;
   8 # redistributions in binary form must reproduce the above copyright
   9 # notice, this list of conditions and the following disclaimer in the
  10 # documentation and/or other materials provided with the distribution;
  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Ron Dreslinski
  28
  29 import m5
  30 from m5.objects import *
  31 import os, optparse, sys
  32 m5.AddToPath('../common')
  33
  34 parser = optparse.OptionParser()
  35
  36 parser.add_option("--caches", action="store_true")
  37 parser.add_option("-t", "--timing", action="store_true")
  38 parser.add_option("-m", "--maxtick", type="int")
  39 parser.add_option("-l", "--maxloads", default = "1000000000000", type="int")
  40 parser.add_option("-n", "--numtesters", default = "8", type="int")
  41 parser.add_option("-p", "--protocol",
  42                   default="moesi",
  43                   help="The coherence protocol to use for the L1'a (i.e. MOESI, MOSI)")
  44
  45 (options, args) = parser.parse_args()
  46
  47 if args:
  48      print "Error: script doesn't take any positional arguments"
  49      sys.exit(1)
  50
  51 # --------------------
  52 # Base L1 Cache
  53 # ====================
  54
  55 class L1(BaseCache):
  56     latency = '1ns'
  57     block_size = 64
  58     mshrs = 12
  59     tgts_per_mshr = 8
  60     protocol = CoherenceProtocol(protocol=options.protocol)
  61
  62 # ----------------------
  63 # Base L2 Cache
  64 # ----------------------
  65
  66 class L2(BaseCache):
  67     block_size = 64
  68     latency = '10ns'
  69     mshrs = 92
  70     tgts_per_mshr = 16
  71     write_buffers = 8
  72
  73 #MAX CORES IS 8 with the false sharing method
  74 if options.numtesters > 8:
  75      print "Error: NUmber of testers limited to 8 because of false sharing"
  76      sys,exit(1)
  77
  78 cpus = [ MemTest(atomic=options.timing, max_loads=options.maxloads,
  79                  percent_functional=50, percent_uncacheable=10,
  80                  progress_interval=1000)
  81          for i in xrange(options.numtesters) ]
  82
  83 # system simulated
  84 system = System(cpu = cpus, funcmem = PhysicalMemory(),
  85                 physmem = PhysicalMemory(latency = "50ps"),
  86                 membus = Bus(clock="500GHz", width=16))
  87
  88 # l2cache & bus
  89 if options.caches:
  90     system.toL2Bus = Bus(clock="500GHz", width=16)
  91     system.l2c = L2(size='64kB', assoc=8)
  92     system.l2c.cpu_side = system.toL2Bus.port
  93
  94     # connect l2c to membus
  95     system.l2c.mem_side = system.membus.port
  96
  97 # add L1 caches
  98 for cpu in cpus:
  99     if options.caches:
 100          cpu.l1c = L1(size = '32kB', assoc = 4)
 101          cpu.test = cpu.l1c.cpu_side
 102          cpu.l1c.mem_side = system.toL2Bus.port
 103     else:
 104          cpu.test = system.membus.port
 105     system.funcmem.port = cpu.functional
 106
 107 # connect memory to membus
 108 system.physmem.port = system.membus.port
 109
 110
 111 # -----------------------
 112 # run simulation
 113 # -----------------------
 114
 115 root = Root( system = system )
 116 if options.timing:
 117     root.system.mem_mode = 'timing'
 118 else:
 119     root.system.mem_mode = 'atomic'
 120
 121 # instantiate configuration
 122 m5.instantiate(root)
 123
 124 # simulate until program terminates
 125 if options.maxtick:
 126     exit_event = m5.simulate(options.maxtick)
 127 else:
 128     exit_event = m5.simulate(10000000000000)
 129
 130 print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()