configs/example/memtest.py

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  38 #
  39 # Authors: Ron Dreslinski
  40 #          Andreas Hansson
  41
  42 import optparse
  43 import sys
  44
  45 import m5
  46 from m5.objects import *
  47
  48 parser = optparse.OptionParser()
  49
  50 parser.add_option("-a", "--atomic", action="store_true",
  51                   help="Use atomic (non-timing) mode")
  52 parser.add_option("-b", "--blocking", action="store_true",
  53                   help="Use blocking caches")
  54 parser.add_option("-l", "--maxloads", metavar="N", default=0,
  55                   help="Stop after N loads")
  56 parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
  57                   metavar="T",
  58                   help="Stop after T ticks")
  59
  60 # This example script stress tests the memory system by creating false
  61 # sharing in a tree topology. At the bottom of the tree is a shared
  62 # memory, and then at each level a number of testers are attached,
  63 # along with a number of caches that them selves fan out to subtrees
  64 # of testers and caches. Thus, it is possible to create a system with
  65 # arbitrarily deep cache hierarchies, sharing or no sharing of caches,
  66 # and testers not only at the L1s, but also at the L2s, L3s etc.
  67 #
  68 # The tree specification consists of two colon-separated lists of one
  69 # or more integers, one for the caches, and one for the testers. The
  70 # first integer is the number of caches/testers closest to main
  71 # memory. Each cache then fans out to a subtree. The last integer in
  72 # the list is the number of caches/testers associated with the
  73 # uppermost level of memory. The other integers (if any) specify the
  74 # number of caches/testers connected at each level of the crossbar
  75 # hierarchy. The tester string should have one element more than the
  76 # cache string as there should always be testers attached to the
  77 # uppermost caches.
  78
  79 parser.add_option("-c", "--caches", type="string", default="2:2:1",
  80                   help="Colon-separated cache hierarchy specification, "
  81                   "see script comments for details "
  82                   "[default: %default]")
  83 parser.add_option("-t", "--testers", type="string", default="1:1:0:2",
  84                   help="Colon-separated tester hierarchy specification, "
  85                   "see script comments for details "
  86                   "[default: %default]")
  87 parser.add_option("-f", "--functional", type="int", default=0,
  88                   metavar="PCT",
  89                   help="Target percentage of functional accesses "
  90                   "[default: %default]")
  91 parser.add_option("-u", "--uncacheable", type="int", default=0,
  92                   metavar="PCT",
  93                   help="Target percentage of uncacheable accesses "
  94                   "[default: %default]")
  95
  96 parser.add_option("--progress", type="int", default=10000,
  97                   metavar="NLOADS",
  98                   help="Progress message interval "
  99                   "[default: %default]")
 100 parser.add_option("--sys-clock", action="store", type="string",
 101                   default='1GHz',
 102                   help = """Top-level clock for blocks running at system
 103                   speed""")
 104
 105 (options, args) = parser.parse_args()
 106
 107 if args:
 108      print "Error: script doesn't take any positional arguments"
 109      sys.exit(1)
 110
 111 block_size = 64
 112
 113 # Start by parsing the command line options and do some basic sanity
 114 # checking
 115 try:
 116      cachespec = [int(x) for x in options.caches.split(':')]
 117      testerspec = [int(x) for x in options.testers.split(':')]
 118 except:
 119      print "Error: Unable to parse caches or testers option"
 120      sys.exit(1)
 121
 122 if len(cachespec) < 1:
 123      print "Error: Must have at least one level of caches"
 124      sys.exit(1)
 125
 126 if len(cachespec) != len(testerspec) - 1:
 127      print "Error: Testers must have one element more than caches"
 128      sys.exit(1)
 129
 130 if testerspec[-1] == 0:
 131      print "Error: Must have testers at the uppermost level"
 132      sys.exit(1)
 133
 134 for t in testerspec:
 135      if t < 0:
 136           print "Error: Cannot have a negative number of testers"
 137           sys.exit(1)
 138
 139 for c in cachespec:
 140      if c < 1:
 141           print "Error: Must have 1 or more caches at each level"
 142           sys.exit(1)
 143
 144 # Determine the tester multiplier for each level as the string
 145 # elements are per subsystem and it fans out
 146 multiplier = [1]
 147 for c in cachespec:
 148      if c < 1:
 149           print "Error: Must have at least one cache per level"
 150      multiplier.append(multiplier[-1] * c)
 151
 152 numtesters = 0
 153 for t, m in zip(testerspec, multiplier):
 154      numtesters += t * m
 155
 156 if numtesters > block_size:
 157      print "Error: Number of testers limited to %s because of false sharing" \
 158            % (block_size)
 159      sys.exit(1)
 160
 161 # Define a prototype L1 cache that we scale for all successive levels
 162 proto_l1 = BaseCache(size = '32kB', assoc = 4,
 163                      hit_latency = 1, response_latency = 1,
 164                      tgts_per_mshr = 8, is_top_level = True)
 165
 166 if options.blocking:
 167      proto_l1.mshrs = 1
 168 else:
 169      proto_l1.mshrs = 4
 170
 171 cache_proto = [proto_l1]
 172
 173 # Now add additional cache levels (if any) by scaling L1 params, the
 174 # first element is Ln, and the last element L1
 175 for scale in cachespec[:-1]:
 176      # Clone previous level and update params
 177      prev = cache_proto[0]
 178      next = prev()
 179      next.size = prev.size * scale
 180      next.hit_latency = prev.hit_latency * 10
 181      next.response_latency = prev.response_latency * 10
 182      next.assoc = prev.assoc * scale
 183      next.mshrs = prev.mshrs * scale
 184      next.is_top_level = False
 185      cache_proto.insert(0, next)
 186
 187 # Make a prototype for the tester to be used throughout
 188 proto_tester = MemTest(max_loads = options.maxloads,
 189                        percent_functional = options.functional,
 190                        percent_uncacheable = options.uncacheable,
 191                        progress_interval = options.progress)
 192
 193 # Set up the system along with a simple memory and reference memory
 194 system = System(physmem = SimpleMemory(),
 195                 cache_line_size = block_size)
 196
 197 system.voltage_domain = VoltageDomain(voltage = '1V')
 198
 199 system.clk_domain = SrcClockDomain(clock =  options.sys_clock,
 200                         voltage_domain = system.voltage_domain)
 201
 202 # For each level, track the next subsys index to use
 203 next_subsys_index = [0] * (len(cachespec) + 1)
 204
 205 # Recursive function to create a sub-tree of the cache and tester
 206 # hierarchy
 207 def make_cache_level(ncaches, prototypes, level, next_cache):
 208      global next_subsys_index, proto_l1, testerspec, proto_tester
 209
 210      index = next_subsys_index[level]
 211      next_subsys_index[level] += 1
 212
 213      # Create a subsystem to contain the crossbar and caches, and
 214      # any testers
 215      subsys = SubSystem()
 216      setattr(system, 'l%dsubsys%d' % (level, index), subsys)
 217
 218      # The levels are indexing backwards through the list
 219      ntesters = testerspec[len(cachespec) - level]
 220
 221      # Scale the progress threshold as testers higher up in the tree
 222      # (smaller level) get a smaller portion of the overall bandwidth,
 223      # and also make the interval of packet injection longer for the
 224      # testers closer to the memory (larger level) to prevent them
 225      # hogging all the bandwidth
 226      limit = (len(cachespec) - level + 1) * 10000000
 227      testers = [proto_tester(interval = 10 * (level * level + 1),
 228                              progress_check = limit) \
 229                      for i in xrange(ntesters)]
 230      if ntesters:
 231           subsys.tester = testers
 232
 233      if level != 0:
 234           # Create a crossbar and add it to the subsystem, note that
 235           # we do this even with a single element on this level
 236           xbar = CoherentXBar(width = 32)
 237           subsys.xbar = xbar
 238           if next_cache:
 239                xbar.master = next_cache.cpu_side
 240
 241           # Create and connect the caches, both the ones fanning out
 242           # to create the tree, and the ones used to connect testers
 243           # on this level
 244           tree_caches = [prototypes[0]() for i in xrange(ncaches[0])]
 245           tester_caches = [proto_l1() for i in xrange(ntesters)]
 246
 247           subsys.cache = tester_caches + tree_caches
 248           for cache in tree_caches:
 249                cache.mem_side = xbar.slave
 250                make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache)
 251           for tester, cache in zip(testers, tester_caches):
 252                tester.port = cache.cpu_side
 253                cache.mem_side = xbar.slave
 254      else:
 255           if not next_cache:
 256                print "Error: No next-level cache at top level"
 257                sys.exit(1)
 258
 259           if ntesters > 1:
 260                # Create a crossbar and add it to the subsystem
 261                xbar = CoherentXBar(width = 32)
 262                subsys.xbar = xbar
 263                xbar.master = next_cache.cpu_side
 264                for tester in testers:
 265                     tester.port = xbar.slave
 266           else:
 267                # Single tester
 268                testers[0].port = next_cache.cpu_side
 269
 270 # Top level call to create the cache hierarchy, bottom up
 271 make_cache_level(cachespec, cache_proto, len(cachespec), None)
 272
 273 # Connect the lowest level crossbar to the memory
 274 last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec))
 275 last_subsys.xbar.master = system.physmem.port
 276
 277 root = Root(full_system = False, system = system)
 278 if options.atomic:
 279     root.system.mem_mode = 'atomic'
 280 else:
 281     root.system.mem_mode = 'timing'
 282
 283 # The system port is never used in the tester so merely connect it
 284 # to avoid problems
 285 root.system.system_port = last_subsys.xbar.slave
 286
 287 # Instantiate configuration
 288 m5.instantiate()
 289
 290 # Simulate until program terminates
 291 exit_event = m5.simulate(options.maxtick)
 292
 293 print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()