configs/example/memtest.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
   4 # Redistribution and use in source and binary forms, with or without
   5 # modification, are permitted provided that the following conditions are
   6 # met: redistributions of source code must retain the above copyright
   7 # notice, this list of conditions and the following disclaimer;
   8 # redistributions in binary form must reproduce the above copyright
   9 # notice, this list of conditions and the following disclaimer in the
  10 # documentation and/or other materials provided with the distribution;
  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Ron Dreslinski
  28
  29 import m5
  30 from m5.objects import *
  31 import os, optparse, sys
  32 m5.AddToPath('../common')
  33
  34 parser = optparse.OptionParser()
  35
  36 parser.add_option("-a", "--atomic", action="store_true",
  37                   help="Use atomic (non-timing) mode")
  38 parser.add_option("-b", "--blocking", action="store_true",
  39                   help="Use blocking caches")
  40 parser.add_option("-l", "--maxloads", metavar="N", default=0,
  41                   help="Stop after N loads")
  42 parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
  43                   metavar="T",
  44                   help="Stop after T ticks")
  45
  46 #
  47 # The "tree" specification is a colon-separated list of one or more
  48 # integers.  The first integer is the number of caches/testers
  49 # connected directly to main memory.  The last integer in the list is
  50 # the number of testers associated with the uppermost level of memory
  51 # (L1 cache, if there are caches, or main memory if no caches).  Thus
  52 # if there is only one integer, there are no caches, and the integer
  53 # specifies the number of testers connected directly to main memory.
  54 # The other integers (if any) specify the number of caches at each
  55 # level of the hierarchy between.
  56 #
  57 # Examples:
  58 #
  59 #  "2:1"    Two caches connected to memory with a single tester behind each
  60 #           (single-level hierarchy, two testers total)
  61 #
  62 #  "2:2:1"  Two-level hierarchy, 2 L1s behind each of 2 L2s, 4 testers total
  63 #
  64 parser.add_option("-t", "--treespec", type="string", default="8:1",
  65                   help="Colon-separated multilevel tree specification, "
  66                   "see script comments for details "
  67                   "[default: %default]")
  68
  69 parser.add_option("--force-bus", action="store_true",
  70                   help="Use bus between levels even with single cache")
  71
  72 parser.add_option("-f", "--functional", type="int", default=0,
  73                   metavar="PCT",
  74                   help="Target percentage of functional accesses "
  75                   "[default: %default]")
  76 parser.add_option("-u", "--uncacheable", type="int", default=0,
  77                   metavar="PCT",
  78                   help="Target percentage of uncacheable accesses "
  79                   "[default: %default]")
  80
  81 parser.add_option("--progress", type="int", default=1000,
  82                   metavar="NLOADS",
  83                   help="Progress message interval "
  84                   "[default: %default]")
  85
  86 (options, args) = parser.parse_args()
  87
  88 if args:
  89      print "Error: script doesn't take any positional arguments"
  90      sys.exit(1)
  91
  92 block_size = 64
  93
  94 try:
  95      treespec = [int(x) for x in options.treespec.split(':')]
  96      numtesters = reduce(lambda x,y: x*y, treespec)
  97 except:
  98      print "Error parsing treespec option"
  99      sys.exit(1)
 100
 101 if numtesters > block_size:
 102      print "Error: Number of testers limited to %s because of false sharing" \
 103            % (block_size)
 104      sys.exit(1)
 105
 106 if len(treespec) < 1:
 107      print "Error parsing treespec"
 108      sys.exit(1)
 109
 110 # define prototype L1 cache
 111 proto_l1 = BaseCache(size = '32kB', assoc = 4, block_size = block_size,
 112                      latency = '1ns', tgts_per_mshr = 8)
 113
 114 if options.blocking:
 115      proto_l1.mshrs = 1
 116 else:
 117      proto_l1.mshrs = 8
 118
 119 # build a list of prototypes, one for each level of treespec, starting
 120 # at the end (last entry is tester objects)
 121 prototypes = [ MemTest(atomic=options.atomic, max_loads=options.maxloads,
 122                        percent_functional=options.functional,
 123                        percent_uncacheable=options.uncacheable,
 124                        progress_interval=options.progress) ]
 125
 126 # next comes L1 cache, if any
 127 if len(treespec) > 1:
 128      prototypes.insert(0, proto_l1)
 129
 130 # now add additional cache levels (if any) by scaling L1 params
 131 while len(prototypes) < len(treespec):
 132      # clone previous level and update params
 133      prev = prototypes[0]
 134      next = prev()
 135      next.size = prev.size * 4
 136      next.latency = prev.latency * 10
 137      next.assoc = prev.assoc * 2
 138      prototypes.insert(0, next)
 139
 140 # system simulated
 141 system = System(funcmem = PhysicalMemory(),
 142                 physmem = PhysicalMemory(latency = "100ns"))
 143
 144 def make_level(spec, prototypes, attach_obj, attach_port):
 145      fanout = spec[0]
 146      parent = attach_obj # use attach obj as config parent too
 147      if len(spec) > 1 and (fanout > 1 or options.force_bus):
 148           new_bus = Bus(clock="500MHz", width=16)
 149           new_bus.port = getattr(attach_obj, attach_port)
 150           parent.cpu_side_bus = new_bus
 151           attach_obj = new_bus
 152           attach_port = "port"
 153      objs = [prototypes[0]() for i in xrange(fanout)]
 154      if len(spec) > 1:
 155           # we just built caches, more levels to go
 156           parent.cache = objs
 157           for cache in objs:
 158                cache.mem_side = getattr(attach_obj, attach_port)
 159                make_level(spec[1:], prototypes[1:], cache, "cpu_side")
 160      else:
 161           # we just built the MemTest objects
 162           parent.cpu = objs
 163           for t in objs:
 164                t.test = getattr(attach_obj, attach_port)
 165                t.functional = system.funcmem.port
 166
 167 make_level(treespec, prototypes, system.physmem, "port")
 168
 169 # -----------------------
 170 # run simulation
 171 # -----------------------
 172
 173 root = Root( system = system )
 174 if options.atomic:
 175     root.system.mem_mode = 'atomic'
 176 else:
 177     root.system.mem_mode = 'timing'
 178
 179 # Not much point in this being higher than the L1 latency
 180 m5.ticks.setGlobalFrequency('1ns')
 181
 182 # instantiate configuration
 183 m5.instantiate(root)
 184
 185 # simulate until program terminates
 186 exit_event = m5.simulate(options.maxtick)
 187
 188 print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()