configs/example/ruby.config

   1 //Default parameters, taken from /athitos/export/08spr_ee382a/sanchezd/runs/gen-scripts/ruby.defaults
   2
   3 //General config
   4 g_DEADLOCK_THRESHOLD: 20000000
   5 RANDOMIZATION: false
   6 g_tester_length: 0
   7 SIMICS_RUBY_MULTIPLIER: 1
   8 OPAL_RUBY_MULTIPLIER: 1
   9 TRANSACTION_TRACE_ENABLED: false
  10 USER_MODE_DATA_ONLY: false
  11 PROFILE_HOT_LINES: false
  12 PROFILE_ALL_INSTRUCTIONS: false
  13 PRINT_INSTRUCTION_TRACE: false
  14 g_DEBUG_CYCLE: 0
  15 PERFECT_MEMORY_SYSTEM: false
  16 PERFECT_MEMORY_SYSTEM_LATENCY: 0
  17 DATA_BLOCK: false
  18
  19 // Line, page sizes
  20 g_DATA_BLOCK_BYTES: 64
  21 g_PAGE_SIZE_BYTES: 8192
  22
  23
  24 g_REPLACEMENT_POLICY: PSEDUO_LRU
  25 // For all caches (sic)
  26
  27 // L1 config
  28 //  32KB, 4-way SA
  29 L1_CACHE_ASSOC: 4
  30 L1_CACHE_NUM_SETS_BITS: 7
  31 //  Single-cycle latency, hits take fastpath
  32 SEQUENCER_TO_CONTROLLER_LATENCY: 1
  33 REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false
  34 //  L1->L2 delays
  35 L1_REQUEST_LATENCY: 1
  36 L1_RESPONSE_LATENCY: 1
  37
  38 // L2 parameters
  39 //  4 MB, 16-way SA
  40 L2_CACHE_ASSOC: 16
  41 L2_CACHE_NUM_SETS_BITS: 12
  42 MAP_L2BANKS_TO_LOWEST_BITS: false
  43 //  Bank latencies
  44 L2_RESPONSE_LATENCY: 10
  45 L2_TAG_LATENCY: 5
  46
  47
  48 // Directory latencies
  49 //  The one that counts, we have perfect dirs
  50 DIRECTORY_CACHE_LATENCY: 6
  51 //  should not be used, but just in case...
  52 DIRECTORY_LATENCY: 6
  53
  54 // Simple network parameters
  55 //  external links
  56 NETWORK_LINK_LATENCY: 1
  57 // intra-chip links
  58 ON_CHIP_LINK_LATENCY: 1
  59
  60 // General latencies
  61 RECYCLE_LATENCY: 1
  62 //Used in MessageBuffer, also MSI_MOSI_CMP dir controller
  63
  64
  65 // Unused parameters, good to define them to really weird things just in case
  66 NULL_LATENCY: 100000
  67 // Only SMP and token CMP protocols
  68 ISSUE_LATENCY: 100000
  69 // Only SMP, example protocols
  70 CACHE_RESPONSE_LATENCY: 100000
  71 // Only SMP protocols
  72 COPY_HEAD_LATENCY: 100000
  73 // In no protocols or ruby code
  74 L2_RECYCLE_LATENCY: 100000
  75 // In no protocols or ruby code
  76 TIMER_LATENCY: 100000
  77 // Not used
  78 TBE_RESPONSE_LATENCY: 100000
  79 // Not used
  80 PERIODIC_TIMER_WAKEUPS: false
  81 // Not used
  82 BLOCK_STC: false
  83 // Not used
  84 SINGLE_ACCESS_L2_BANKS: false
  85 // Not used
  86
  87 // Main memory latency
  88 MEMORY_RESPONSE_LATENCY_MINUS_2: 448 //not used in _m, see below
  89
  90 PROFILE_EXCEPTIONS: false
  91 PROFILE_XACT: false
  92 PROFILE_NONXACT: true
  93 XACT_DEBUG: false
  94 XACT_DEBUG_LEVEL: 1
  95 XACT_MEMORY: false
  96 XACT_ENABLE_TOURMALINE: false
  97 XACT_NUM_CURRENT: 0
  98 XACT_LAST_UPDATE: 0
  99 XACT_ISOLATION_CHECK: false
 100 PERFECT_FILTER: true
 101 READ_WRITE_FILTER: Perfect_
 102 PERFECT_VIRTUAL_FILTER: true
 103 VIRTUAL_READ_WRITE_FILTER: Perfect_
 104 PERFECT_SUMMARY_FILTER: true
 105 SUMMARY_READ_WRITE_FILTER: Perfect_
 106 XACT_EAGER_CD: true
 107 XACT_LAZY_VM: false
 108 XACT_CONFLICT_RES: BASE
 109 XACT_COMMIT_TOKEN_LATENCY: 0
 110 XACT_NO_BACKOFF: false
 111 XACT_LOG_BUFFER_SIZE: 0
 112 XACT_STORE_PREDICTOR_HISTORY: 0
 113 XACT_STORE_PREDICTOR_ENTRIES: 0
 114 XACT_STORE_PREDICTOR_THRESHOLD: 0
 115 XACT_FIRST_ACCESS_COST: 0
 116 XACT_FIRST_PAGE_ACCESS_COST: 0
 117 ENABLE_MAGIC_WAITING: false
 118 ENABLE_WATCHPOINT: false
 119 XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false
 120 ATMTP_ENABLED: false
 121 ATMTP_ABORT_ON_NON_XACT_INST: false
 122 ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false
 123 ATMTP_XACT_MAX_STORES: 0
 124 ATMTP_DEBUG_LEVEL: 0
 125 XACT_LENGTH: 0
 126 XACT_SIZE: 0
 127 ABORT_RETRY_TIME: 0
 128
 129
 130 // Allowed parallelism in controllers
 131 L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
 132 L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 1000
 133 DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 1000
 134 g_SEQUENCER_OUTSTANDING_REQUESTS: 16
 135
 136 //TBEs == MSHRs (global)
 137 NUMBER_OF_TBES: 128
 138 NUMBER_OF_L1_TBES: 32
 139 // unused in CMP protocols
 140 NUMBER_OF_L2_TBES: 32
 141 // unused in CMP protocols
 142
 143
 144 // TSO & WBuffer params (unused)
 145 FINITE_BUFFERING: false
 146 FINITE_BUFFER_SIZE: 3
 147 PROCESSOR_BUFFER_SIZE: 10
 148 PROTOCOL_BUFFER_SIZE: 32
 149 TSO: false
 150
 151 // General network params
 152 g_endpoint_bandwidth: 10000
 153 g_adaptive_routing: true
 154 NUMBER_OF_VIRTUAL_NETWORKS: 5
 155 FAN_OUT_DEGREE: 4
 156 //  for HIERARCHICAL_SWITCH
 157
 158
 159 // Detailed Memory Controller Params (only used in _m protocols)
 160 MEM_BUS_CYCLE_MULTIPLIER: 5
 161 BANKS_PER_RANK: 8
 162 RANKS_PER_DIMM: 2
 163 DIMMS_PER_CHANNEL: 2
 164 BANK_BIT_0: 8
 165 RANK_BIT_0: 11
 166 DIMM_BIT_0: 12
 167
 168 BANK_QUEUE_SIZE: 12
 169 BANK_BUSY_TIME: 22
 170 RANK_RANK_DELAY: 2
 171 READ_WRITE_DELAY: 3
 172 BASIC_BUS_BUSY_TIME: 3
 173 MEM_CTL_LATENCY: 20
 174 REFRESH_PERIOD: 3120
 175 TFAW: 0
 176 //flip a coin to delay requests by one cycle, introduces non-determinism
 177 MEM_RANDOM_ARBITRATE: 50
 178 MEM_FIXED_DELAY: 0
 179
 180
 181 //Configuration-specific parameters
 182 g_NUM_PROCESSORS: 1
 183 g_NUM_CHIPS: 1
 184 g_PROCS_PER_CHIP: 1
 185 g_NUM_L2_BANKS: 1
 186 g_NUM_MEMORIES: 4
 187 g_PRINT_TOPOLOGY: true
 188 g_GARNET_NETWORK: true
 189 g_DETAIL_NETWORK: true
 190 g_FLIT_SIZE: 8