1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
2 # Copyright (c) 2009 Advanced Micro Devices, Inc.
5 # Redistribution and use in source and binary forms, with or without
6 # modification, are permitted provided that the following conditions are
7 # met: redistributions of source code must retain the above copyright
8 # notice, this list of conditions and the following disclaimer;
9 # redistributions in binary form must reproduce the above copyright
10 # notice, this list of conditions and the following disclaimer in the
11 # documentation and/or other materials provided with the distribution;
12 # neither the name of the copyright holders nor the names of its
13 # contributors may be used to endorse or promote products derived from
14 # this software without specific prior written permission.
16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 from __future__
import print_function
29 from __future__
import absolute_import
32 from m5
.objects
import *
33 from m5
.defines
import buildEnv
34 from m5
.util
import addToPath
35 import os
, optparse
, sys
39 from common
import Options
42 # Get paths we might need. It's expected this file is in m5/configs/example.
43 config_path
= os
.path
.dirname(os
.path
.abspath(__file__
))
44 config_root
= os
.path
.dirname(config_path
)
45 m5_root
= os
.path
.dirname(config_root
)
47 parser
= optparse
.OptionParser()
48 Options
.addNoISAOptions(parser
)
50 parser
.add_option("--requests", metavar
="N", default
=100,
51 help="Stop after N requests")
52 parser
.add_option("-f", "--wakeup_freq", metavar
="N", default
=10,
53 help="Wakeup every N cycles")
54 parser
.add_option("--test-type", type="choice", default
="SeriesGetx",
55 choices
= ["SeriesGetx", "SeriesGets", "SeriesGetMixed",
57 help = "Type of test")
58 parser
.add_option("--percent-writes", type="int", default
=100,
59 help="percentage of accesses that should be writes")
62 # Add the ruby specific and protocol specific options
64 Ruby
.define_options(parser
)
65 (options
, args
) = parser
.parse_args()
68 print("Error: script doesn't take any positional arguments")
72 # Select the direct test generator
74 if options
.test_type
== "SeriesGetx":
75 generator
= SeriesRequestGenerator(num_cpus
= options
.num_cpus
,
77 elif options
.test_type
== "SeriesGets":
78 generator
= SeriesRequestGenerator(num_cpus
= options
.num_cpus
,
80 elif options
.test_type
== "SeriesGetMixed":
81 generator
= SeriesRequestGenerator(num_cpus
= options
.num_cpus
,
82 percent_writes
= options
.percent_writes
)
83 elif options
.test_type
== "Invalidate":
84 generator
= InvalidateGenerator(num_cpus
= options
.num_cpus
)
86 print("Error: unknown direct test generator")
89 # Create the M5 system.
90 system
= System(mem_ranges
= [AddrRange(options
.mem_size
)])
93 # Create a top-level voltage domain and clock domain
94 system
.voltage_domain
= VoltageDomain(voltage
= options
.sys_voltage
)
96 system
.clk_domain
= SrcClockDomain(clock
= options
.sys_clock
,
97 voltage_domain
= system
.voltage_domain
)
99 # Create the ruby random tester
100 system
.cpu
= RubyDirectedTester(requests_to_complete
= options
.requests
,
101 generator
= generator
)
103 Ruby
.create_system(options
, False, system
)
105 # Since Ruby runs at an independent frequency, create a seperate clock
106 system
.ruby
.clk_domain
= SrcClockDomain(clock
= options
.ruby_clock
,
107 voltage_domain
= system
.voltage_domain
)
109 assert(options
.num_cpus
== len(system
.ruby
._cpu
_ports
))
111 for ruby_port
in system
.ruby
._cpu
_ports
:
113 # Tie the ruby tester ports to the ruby cpu ports
115 system
.cpu
.cpuPort
= ruby_port
.slave
117 # -----------------------
119 # -----------------------
121 root
= Root( full_system
= False, system
= system
)
122 root
.system
.mem_mode
= 'timing'
124 # Not much point in this being higher than the L1 latency
125 m5
.ticks
.setGlobalFrequency('1ns')
127 # instantiate configuration
130 # simulate until program terminates
131 exit_event
= m5
.simulate(options
.abs_max_tick
)
133 print('Exiting @ tick', m5
.curTick(), 'because', exit_event
.getCause())