MEM: Fix master/slave ports in Ruby and non-regression scripts
[gem5.git] / configs / example / ruby_direct_test.py
1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
2 # Copyright (c) 2009 Advanced Micro Devices, Inc.
3 # All rights reserved.
4 #
5 # Redistribution and use in source and binary forms, with or without
6 # modification, are permitted provided that the following conditions are
7 # met: redistributions of source code must retain the above copyright
8 # notice, this list of conditions and the following disclaimer;
9 # redistributions in binary form must reproduce the above copyright
10 # notice, this list of conditions and the following disclaimer in the
11 # documentation and/or other materials provided with the distribution;
12 # neither the name of the copyright holders nor the names of its
13 # contributors may be used to endorse or promote products derived from
14 # this software without specific prior written permission.
15 #
16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #
28 # Authors: Ron Dreslinski
29 # Brad Beckmann
30
31 import m5
32 from m5.objects import *
33 from m5.defines import buildEnv
34 from m5.util import addToPath
35 import os, optparse, sys
36 addToPath('../common')
37 addToPath('../ruby')
38
39 import Ruby
40
41 # Get paths we might need. It's expected this file is in m5/configs/example.
42 config_path = os.path.dirname(os.path.abspath(__file__))
43 config_root = os.path.dirname(config_path)
44 m5_root = os.path.dirname(config_root)
45
46 parser = optparse.OptionParser()
47
48 parser.add_option("-l", "--requests", metavar="N", default=100,
49 help="Stop after N requests")
50 parser.add_option("-f", "--wakeup_freq", metavar="N", default=10,
51 help="Wakeup every N cycles")
52 parser.add_option("--test-type", type="string", default="SeriesGetx",
53 help="SeriesGetx|SeriesGets|Invalidate")
54
55 #
56 # Add the ruby specific and protocol specific options
57 #
58 Ruby.define_options(parser)
59
60 execfile(os.path.join(config_root, "common", "Options.py"))
61
62 (options, args) = parser.parse_args()
63
64 if args:
65 print "Error: script doesn't take any positional arguments"
66 sys.exit(1)
67
68 #
69 # Select the direct test generator
70 #
71 if options.test_type == "SeriesGetx":
72 generator = SeriesRequestGenerator(num_cpus = options.num_cpus,
73 issue_writes = True)
74 elif options.test_type == "SeriesGets":
75 generator = SeriesRequestGenerator(num_cpus = options.num_cpus,
76 issue_writes = False)
77 elif options.test_type == "Invalidate":
78 generator = InvalidateGenerator(num_cpus = options.num_cpus)
79 else:
80 print "Error: unknown direct test generator"
81 sys.exit(1)
82
83 #
84 # Create the M5 system. Note that the PhysicalMemory Object isn't
85 # actually used by the rubytester, but is included to support the
86 # M5 memory size == Ruby memory size checks
87 #
88 system = System(physmem = PhysicalMemory())
89
90 #
91 # Create the ruby random tester
92 #
93 system.tester = RubyDirectedTester(requests_to_complete = \
94 options.requests,
95 generator = generator)
96
97 Ruby.create_system(options, system)
98
99 assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
100
101 for ruby_port in system.ruby._cpu_ruby_ports:
102 #
103 # Tie the ruby tester ports to the ruby cpu ports
104 #
105 system.tester.cpuPort = ruby_port.slave
106
107 # -----------------------
108 # run simulation
109 # -----------------------
110
111 root = Root( full_system = False, system = system )
112 root.system.mem_mode = 'timing'
113
114 # Not much point in this being higher than the L1 latency
115 m5.ticks.setGlobalFrequency('1ns')
116
117 # instantiate configuration
118 m5.instantiate()
119
120 # simulate until program terminates
121 exit_event = m5.simulate(options.maxtick)
122
123 print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()