configs/example/ruby_fs.py

   1 # Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
   2 # All rights reserved.
   3 #
   4 # Redistribution and use in source and binary forms, with or without
   5 # modification, are permitted provided that the following conditions are
   6 # met: redistributions of source code must retain the above copyright
   7 # notice, this list of conditions and the following disclaimer;
   8 # redistributions in binary form must reproduce the above copyright
   9 # notice, this list of conditions and the following disclaimer in the
  10 # documentation and/or other materials provided with the distribution;
  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Brad Beckmann
  28
  29 #
  30 # Full system configuraiton for ruby
  31 #
  32
  33 import optparse
  34 import sys
  35
  36 import m5
  37 from m5.defines import buildEnv
  38 from m5.objects import *
  39 from m5.util import addToPath, fatal
  40
  41 addToPath('../common')
  42 addToPath('../ruby')
  43 addToPath('../topologies')
  44
  45 import Ruby
  46
  47 from FSConfig import *
  48 from SysPaths import *
  49 from Benchmarks import *
  50 import Options
  51 import Simulation
  52
  53 parser = optparse.OptionParser()
  54 Options.addCommonOptions(parser)
  55 Options.addFSOptions(parser)
  56
  57 # Add the ruby specific and protocol specific options
  58 Ruby.define_options(parser)
  59
  60 (options, args) = parser.parse_args()
  61 options.ruby = True
  62
  63 if args:
  64     print "Error: script doesn't take any positional arguments"
  65     sys.exit(1)
  66
  67 if options.benchmark:
  68     try:
  69         bm = Benchmarks[options.benchmark]
  70     except KeyError:
  71         print "Error benchmark %s has not been defined." % options.benchmark
  72         print "Valid benchmarks are: %s" % DefinedBenchmarks
  73         sys.exit(1)
  74 else:
  75     bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
  76
  77 # Check for timing mode because ruby does not support atomic accesses
  78 if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
  79     print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
  80     sys.exit(1)
  81 (CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
  82
  83 CPUClass.clock = options.clock
  84
  85 if buildEnv['TARGET_ISA'] == "alpha":
  86     system = makeLinuxAlphaRubySystem(test_mem_mode, bm[0])
  87 elif buildEnv['TARGET_ISA'] == "x86":
  88     system = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], True)
  89     Simulation.setWorkCountOptions(system, options)
  90 else:
  91     fatal("incapable of building non-alpha or non-x86 full system!")
  92
  93 if options.kernel is not None:
  94     system.kernel = binary(options.kernel)
  95
  96 if options.script is not None:
  97     system.readfile = options.script
  98
  99 system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
 100 Ruby.create_system(options, system, system.piobus, system._dma_ports)
 101
 102 for (i, cpu) in enumerate(system.cpu):
 103     #
 104     # Tie the cpu ports to the correct ruby system ports
 105     #
 106     cpu.createThreads()
 107     cpu.createInterruptController()
 108     cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
 109     cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
 110     if buildEnv['TARGET_ISA'] == "x86":
 111         cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave
 112         cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave
 113         cpu.interrupts.pio = system.piobus.master
 114         cpu.interrupts.int_master = system.piobus.slave
 115         cpu.interrupts.int_slave = system.piobus.master
 116
 117     system.ruby._cpu_ruby_ports[i].access_phys_mem = True
 118
 119 root = Root(full_system = True, system = system)
 120 Simulation.run(options, root, system, FutureClass)