mem: Move crossbar default latencies to subclasses
[gem5.git] / configs / example / ruby_mem_test.py
1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
2 # Copyright (c) 2009 Advanced Micro Devices, Inc.
3 # All rights reserved.
4 #
5 # Redistribution and use in source and binary forms, with or without
6 # modification, are permitted provided that the following conditions are
7 # met: redistributions of source code must retain the above copyright
8 # notice, this list of conditions and the following disclaimer;
9 # redistributions in binary form must reproduce the above copyright
10 # notice, this list of conditions and the following disclaimer in the
11 # documentation and/or other materials provided with the distribution;
12 # neither the name of the copyright holders nor the names of its
13 # contributors may be used to endorse or promote products derived from
14 # this software without specific prior written permission.
15 #
16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #
28 # Authors: Ron Dreslinski
29 # Brad Beckmann
30
31 import m5
32 from m5.objects import *
33 from m5.defines import buildEnv
34 from m5.util import addToPath
35 import os, optparse, sys
36 addToPath('../common')
37 addToPath('../ruby')
38 addToPath('../topologies')
39
40 import Options
41 import Ruby
42
43 # Get paths we might need. It's expected this file is in m5/configs/example.
44 config_path = os.path.dirname(os.path.abspath(__file__))
45 config_root = os.path.dirname(config_path)
46
47 parser = optparse.OptionParser()
48 Options.addCommonOptions(parser)
49
50 parser.add_option("--maxloads", metavar="N", default=0,
51 help="Stop after N loads")
52 parser.add_option("--progress", type="int", default=1000,
53 metavar="NLOADS",
54 help="Progress message interval "
55 "[default: %default]")
56 parser.add_option("--num-dmas", type="int", default=0, help="# of dma testers")
57 parser.add_option("--functional", type="int", default=0,
58 help="percentage of accesses that should be functional")
59 parser.add_option("--suppress-func-warnings", action="store_true",
60 help="suppress warnings when functional accesses fail")
61
62 #
63 # Add the ruby specific and protocol specific options
64 #
65 Ruby.define_options(parser)
66
67 execfile(os.path.join(config_root, "common", "Options.py"))
68
69 (options, args) = parser.parse_args()
70
71 #
72 # Set the default cache size and associativity to be very small to encourage
73 # races between requests and writebacks.
74 #
75 options.l1d_size="256B"
76 options.l1i_size="256B"
77 options.l2_size="512B"
78 options.l3_size="1kB"
79 options.l1d_assoc=2
80 options.l1i_assoc=2
81 options.l2_assoc=2
82 options.l3_assoc=2
83
84 if args:
85 print "Error: script doesn't take any positional arguments"
86 sys.exit(1)
87
88 block_size = 64
89
90 if options.num_cpus > block_size:
91 print "Error: Number of testers %d limited to %d because of false sharing" \
92 % (options.num_cpus, block_size)
93 sys.exit(1)
94
95 #
96 # Currently ruby does not support atomic or uncacheable accesses
97 #
98 cpus = [ MemTest(atomic = False,
99 max_loads = options.maxloads,
100 issue_dmas = False,
101 percent_functional = options.functional,
102 percent_uncacheable = 0,
103 progress_interval = options.progress,
104 suppress_func_warnings = options.suppress_func_warnings) \
105 for i in xrange(options.num_cpus) ]
106
107 system = System(cpu = cpus,
108 funcmem = SimpleMemory(in_addr_map = False),
109 funcbus = IOXBar(),
110 clk_domain = SrcClockDomain(clock = options.sys_clock),
111 mem_ranges = [AddrRange(options.mem_size)])
112
113 if options.num_dmas > 0:
114 dmas = [ MemTest(atomic = False,
115 max_loads = options.maxloads,
116 issue_dmas = True,
117 percent_functional = 0,
118 percent_uncacheable = 0,
119 progress_interval = options.progress,
120 suppress_func_warnings =
121 not options.suppress_func_warnings) \
122 for i in xrange(options.num_dmas) ]
123 system.dma_devices = dmas
124 else:
125 dmas = []
126
127 dma_ports = []
128 for (i, dma) in enumerate(dmas):
129 dma_ports.append(dma.test)
130 Ruby.create_system(options, False, system, dma_ports = dma_ports)
131
132 # Create a top-level voltage domain and clock domain
133 system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
134 system.clk_domain = SrcClockDomain(clock = options.sys_clock,
135 voltage_domain = system.voltage_domain)
136 # Create a seperate clock domain for Ruby
137 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
138 voltage_domain = system.voltage_domain)
139
140 #
141 # The tester is most effective when randomization is turned on and
142 # artifical delay is randomly inserted on messages
143 #
144 system.ruby.randomization = True
145
146 assert(len(cpus) == len(system.ruby._cpu_ports))
147
148 for (i, cpu) in enumerate(cpus):
149 #
150 # Tie the cpu memtester ports to the correct system ports
151 #
152 cpu.test = system.ruby._cpu_ports[i].slave
153 cpu.functional = system.funcbus.slave
154
155 #
156 # Since the memtester is incredibly bursty, increase the deadlock
157 # threshold to 5 million cycles
158 #
159 system.ruby._cpu_ports[i].deadlock_threshold = 5000000
160
161 for (i, dma) in enumerate(dmas):
162 #
163 # Tie the dma memtester ports to the correct functional port
164 # Note that the test port has already been connected to the dma_sequencer
165 #
166 dma.functional = system.funcbus.slave
167
168 # connect reference memory to funcbus
169 system.funcbus.master = system.funcmem.port
170
171 # -----------------------
172 # run simulation
173 # -----------------------
174
175 root = Root( full_system = False, system = system )
176 root.system.mem_mode = 'timing'
177
178 # Not much point in this being higher than the L1 latency
179 m5.ticks.setGlobalFrequency('1ns')
180
181 # instantiate configuration
182 m5.instantiate()
183
184 # simulate until program terminates
185 exit_event = m5.simulate(options.abs_max_tick)
186
187 print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()