Merge branch 'release-staging-v20.0.0.0' into develop
[gem5.git] / configs / example / ruby_random_test.py
1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
2 # Copyright (c) 2009 Advanced Micro Devices, Inc.
3 # All rights reserved.
4 #
5 # Redistribution and use in source and binary forms, with or without
6 # modification, are permitted provided that the following conditions are
7 # met: redistributions of source code must retain the above copyright
8 # notice, this list of conditions and the following disclaimer;
9 # redistributions in binary form must reproduce the above copyright
10 # notice, this list of conditions and the following disclaimer in the
11 # documentation and/or other materials provided with the distribution;
12 # neither the name of the copyright holders nor the names of its
13 # contributors may be used to endorse or promote products derived from
14 # this software without specific prior written permission.
15 #
16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
28 from __future__ import print_function
29 from __future__ import absolute_import
30
31 import m5
32 from m5.objects import *
33 from m5.defines import buildEnv
34 from m5.util import addToPath
35 import os, optparse, sys
36
37 addToPath('../')
38
39 from common import Options
40 from ruby import Ruby
41
42 # Get paths we might need. It's expected this file is in m5/configs/example.
43 config_path = os.path.dirname(os.path.abspath(__file__))
44 config_root = os.path.dirname(config_path)
45 m5_root = os.path.dirname(config_root)
46
47 parser = optparse.OptionParser()
48 Options.addNoISAOptions(parser)
49
50 parser.add_option("--maxloads", metavar="N", default=100,
51 help="Stop after N loads")
52 parser.add_option("-f", "--wakeup_freq", metavar="N", default=10,
53 help="Wakeup every N cycles")
54
55 #
56 # Add the ruby specific and protocol specific options
57 #
58 Ruby.define_options(parser)
59
60 exec(compile( \
61 open(os.path.join(config_root, "common", "Options.py")).read(), \
62 os.path.join(config_root, "common", "Options.py"), 'exec'))
63
64 (options, args) = parser.parse_args()
65
66 #
67 # Set the default cache size and associativity to be very small to encourage
68 # races between requests and writebacks.
69 #
70 options.l1d_size="256B"
71 options.l1i_size="256B"
72 options.l2_size="512B"
73 options.l3_size="1kB"
74 options.l1d_assoc=2
75 options.l1i_assoc=2
76 options.l2_assoc=2
77 options.l3_assoc=2
78
79 if args:
80 print("Error: script doesn't take any positional arguments")
81 sys.exit(1)
82
83 #
84 # Create the ruby random tester
85 #
86
87 # Check the protocol
88 check_flush = False
89 if buildEnv['PROTOCOL'] == 'MOESI_hammer':
90 check_flush = True
91
92 tester = RubyTester(check_flush = check_flush,
93 checks_to_complete = options.maxloads,
94 wakeup_frequency = options.wakeup_freq)
95
96 #
97 # Create the M5 system. Note that the Memory Object isn't
98 # actually used by the rubytester, but is included to support the
99 # M5 memory size == Ruby memory size checks
100 #
101 system = System(cpu = tester, mem_ranges = [AddrRange(options.mem_size)])
102
103 # Create a top-level voltage domain and clock domain
104 system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
105
106 system.clk_domain = SrcClockDomain(clock = options.sys_clock,
107 voltage_domain = system.voltage_domain)
108
109 Ruby.create_system(options, False, system)
110
111 # Create a seperate clock domain for Ruby
112 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
113 voltage_domain = system.voltage_domain)
114
115 assert(options.num_cpus == len(system.ruby._cpu_ports))
116
117 tester.num_cpus = len(system.ruby._cpu_ports)
118
119 #
120 # The tester is most effective when randomization is turned on and
121 # artifical delay is randomly inserted on messages
122 #
123 system.ruby.randomization = True
124
125 for ruby_port in system.ruby._cpu_ports:
126 #
127 # Tie the ruby tester ports to the ruby cpu read and write ports
128 #
129 if ruby_port.support_data_reqs and ruby_port.support_inst_reqs:
130 tester.cpuInstDataPort = ruby_port.slave
131 elif ruby_port.support_data_reqs:
132 tester.cpuDataPort = ruby_port.slave
133 elif ruby_port.support_inst_reqs:
134 tester.cpuInstPort = ruby_port.slave
135
136 # Do not automatically retry stalled Ruby requests
137 ruby_port.no_retry_on_stall = True
138
139 #
140 # Tell each sequencer this is the ruby tester so that it
141 # copies the subblock back to the checker
142 #
143 ruby_port.using_ruby_tester = True
144
145 # -----------------------
146 # run simulation
147 # -----------------------
148
149 root = Root( full_system = False, system = system )
150 root.system.mem_mode = 'timing'
151
152 # Not much point in this being higher than the L1 latency
153 m5.ticks.setGlobalFrequency('1ns')
154
155 # instantiate configuration
156 m5.instantiate()
157
158 # simulate until program terminates
159 exit_event = m5.simulate(options.abs_max_tick)
160
161 print('Exiting @ tick', m5.curTick(), 'because', exit_event.getCause())