configs/example/se.py

   1 # Copyright (c) 2012-2013 ARM Limited
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   3 #
   4 # The license below extends only to copyright in the software and shall
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  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Copyright (c) 2006-2008 The Regents of The University of Michigan
  14 # All rights reserved.
  15 #
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  17 # modification, are permitted provided that the following conditions are
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  37 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38 #
  39 # Authors: Steve Reinhardt
  40
  41 # Simple test script
  42 #
  43 # "m5 test.py"
  44
  45 import optparse
  46 import sys
  47 import os
  48
  49 import m5
  50 from m5.defines import buildEnv
  51 from m5.objects import *
  52 from m5.util import addToPath, fatal
  53
  54 addToPath('../common')
  55 addToPath('../ruby')
  56
  57 import Options
  58 import Ruby
  59 import Simulation
  60 import CacheConfig
  61 import MemConfig
  62 from Caches import *
  63 from cpu2000 import *
  64
  65 # Check if KVM support has been enabled, we might need to do VM
  66 # configuration if that's the case.
  67 have_kvm_support = 'BaseKvmCPU' in globals()
  68 def is_kvm_cpu(cpu_class):
  69     return have_kvm_support and cpu_class != None and \
  70         issubclass(cpu_class, BaseKvmCPU)
  71
  72 def get_processes(options):
  73     """Interprets provided options and returns a list of processes"""
  74
  75     multiprocesses = []
  76     inputs = []
  77     outputs = []
  78     errouts = []
  79     pargs = []
  80
  81     workloads = options.cmd.split(';')
  82     if options.input != "":
  83         inputs = options.input.split(';')
  84     if options.output != "":
  85         outputs = options.output.split(';')
  86     if options.errout != "":
  87         errouts = options.errout.split(';')
  88     if options.options != "":
  89         pargs = options.options.split(';')
  90
  91     idx = 0
  92     for wrkld in workloads:
  93         process = LiveProcess()
  94         process.executable = wrkld
  95         process.cwd = os.getcwd()
  96
  97         if options.env:
  98             with open(options.env, 'r') as f:
  99                 process.env = [line.rstrip() for line in f]
 100
 101         if len(pargs) > idx:
 102             process.cmd = [wrkld] + pargs[idx].split()
 103         else:
 104             process.cmd = [wrkld]
 105
 106         if len(inputs) > idx:
 107             process.input = inputs[idx]
 108         if len(outputs) > idx:
 109             process.output = outputs[idx]
 110         if len(errouts) > idx:
 111             process.errout = errouts[idx]
 112
 113         multiprocesses.append(process)
 114         idx += 1
 115
 116     if options.smt:
 117         assert(options.cpu_type == "detailed")
 118         return multiprocesses, idx
 119     else:
 120         return multiprocesses, 1
 121
 122
 123 parser = optparse.OptionParser()
 124 Options.addCommonOptions(parser)
 125 Options.addSEOptions(parser)
 126
 127 if '--ruby' in sys.argv:
 128     Ruby.define_options(parser)
 129
 130 (options, args) = parser.parse_args()
 131
 132 if args:
 133     print "Error: script doesn't take any positional arguments"
 134     sys.exit(1)
 135
 136 multiprocesses = []
 137 numThreads = 1
 138
 139 if options.bench:
 140     apps = options.bench.split("-")
 141     if len(apps) != options.num_cpus:
 142         print "number of benchmarks not equal to set num_cpus!"
 143         sys.exit(1)
 144
 145     for app in apps:
 146         try:
 147             if buildEnv['TARGET_ISA'] == 'alpha':
 148                 exec("workload = %s('alpha', 'tru64', '%s')" % (
 149                         app, options.spec_input))
 150             elif buildEnv['TARGET_ISA'] == 'arm':
 151                 exec("workload = %s('arm_%s', 'linux', '%s')" % (
 152                         app, options.arm_iset, options.spec_input))
 153             else:
 154                 exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % (
 155                         app, options.spec_input))
 156             multiprocesses.append(workload.makeLiveProcess())
 157         except:
 158             print >>sys.stderr, "Unable to find workload for %s: %s" % (
 159                     buildEnv['TARGET_ISA'], app)
 160             sys.exit(1)
 161 elif options.cmd:
 162     multiprocesses, numThreads = get_processes(options)
 163 else:
 164     print >> sys.stderr, "No workload specified. Exiting!\n"
 165     sys.exit(1)
 166
 167
 168 (CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
 169 CPUClass.numThreads = numThreads
 170
 171 # Check -- do not allow SMT with multiple CPUs
 172 if options.smt and options.num_cpus > 1:
 173     fatal("You cannot use SMT with multiple CPUs!")
 174
 175 np = options.num_cpus
 176 system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
 177                 mem_mode = test_mem_mode,
 178                 mem_ranges = [AddrRange(options.mem_size)],
 179                 cache_line_size = options.cacheline_size)
 180
 181 if numThreads > 1:
 182     system.multi_thread = True
 183
 184 # Create a top-level voltage domain
 185 system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
 186
 187 # Create a source clock for the system and set the clock period
 188 system.clk_domain = SrcClockDomain(clock =  options.sys_clock,
 189                                    voltage_domain = system.voltage_domain)
 190
 191 # Create a CPU voltage domain
 192 system.cpu_voltage_domain = VoltageDomain()
 193
 194 # Create a separate clock domain for the CPUs
 195 system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
 196                                        voltage_domain =
 197                                        system.cpu_voltage_domain)
 198
 199 # All cpus belong to a common cpu_clk_domain, therefore running at a common
 200 # frequency.
 201 for cpu in system.cpu:
 202     cpu.clk_domain = system.cpu_clk_domain
 203
 204 if is_kvm_cpu(CPUClass) or is_kvm_cpu(FutureClass):
 205     if buildEnv['TARGET_ISA'] == 'x86':
 206         system.vm = KvmVM()
 207         for process in multiprocesses:
 208             process.useArchPT = True
 209             process.kvmInSE = True
 210     else:
 211         fatal("KvmCPU can only be used in SE mode with x86")
 212
 213 # Sanity check
 214 if options.fastmem:
 215     if CPUClass != AtomicSimpleCPU:
 216         fatal("Fastmem can only be used with atomic CPU!")
 217     if (options.caches or options.l2cache):
 218         fatal("You cannot use fastmem in combination with caches!")
 219
 220 if options.simpoint_profile:
 221     if not options.fastmem:
 222         # Atomic CPU checked with fastmem option already
 223         fatal("SimPoint generation should be done with atomic cpu and fastmem")
 224     if np > 1:
 225         fatal("SimPoint generation not supported with more than one CPUs")
 226
 227 for i in xrange(np):
 228     if options.smt:
 229         system.cpu[i].workload = multiprocesses
 230     elif len(multiprocesses) == 1:
 231         system.cpu[i].workload = multiprocesses[0]
 232     else:
 233         system.cpu[i].workload = multiprocesses[i]
 234
 235     if options.fastmem:
 236         system.cpu[i].fastmem = True
 237
 238     if options.simpoint_profile:
 239         system.cpu[i].addSimPointProbe(options.simpoint_interval)
 240
 241     if options.checker:
 242         system.cpu[i].addCheckerCpu()
 243
 244     system.cpu[i].createThreads()
 245
 246 if options.ruby:
 247     if options.cpu_type == "atomic" or options.cpu_type == "AtomicSimpleCPU":
 248         print >> sys.stderr, "Ruby does not work with atomic cpu!!"
 249         sys.exit(1)
 250
 251     Ruby.create_system(options, False, system)
 252     assert(options.num_cpus == len(system.ruby._cpu_ports))
 253
 254     system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
 255                                         voltage_domain = system.voltage_domain)
 256     for i in xrange(np):
 257         ruby_port = system.ruby._cpu_ports[i]
 258
 259         # Create the interrupt controller and connect its ports to Ruby
 260         # Note that the interrupt controller is always present but only
 261         # in x86 does it have message ports that need to be connected
 262         system.cpu[i].createInterruptController()
 263
 264         # Connect the cpu's cache ports to Ruby
 265         system.cpu[i].icache_port = ruby_port.slave
 266         system.cpu[i].dcache_port = ruby_port.slave
 267         if buildEnv['TARGET_ISA'] == 'x86':
 268             system.cpu[i].interrupts[0].pio = ruby_port.master
 269             system.cpu[i].interrupts[0].int_master = ruby_port.slave
 270             system.cpu[i].interrupts[0].int_slave = ruby_port.master
 271             system.cpu[i].itb.walker.port = ruby_port.slave
 272             system.cpu[i].dtb.walker.port = ruby_port.slave
 273 else:
 274     MemClass = Simulation.setMemClass(options)
 275     system.membus = SystemXBar()
 276     system.system_port = system.membus.slave
 277     CacheConfig.config_cache(options, system)
 278     MemConfig.config_mem(options, system)
 279
 280 root = Root(full_system = False, system = system)
 281 Simulation.run(options, root, system, FutureClass)