configs/example/se.py

   1 # Copyright (c) 2012 ARM Limited
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  11 # modified or unmodified, in source code or in binary form.
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  13 # Copyright (c) 2006-2008 The Regents of The University of Michigan
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  38 #
  39 # Authors: Steve Reinhardt
  40
  41 # Simple test script
  42 #
  43 # "m5 test.py"
  44
  45 import optparse
  46 import sys
  47
  48 import m5
  49 from m5.defines import buildEnv
  50 from m5.objects import *
  51 from m5.util import addToPath, fatal
  52
  53 addToPath('../common')
  54 addToPath('../ruby')
  55
  56 import Options
  57 import Ruby
  58 import Simulation
  59 import CacheConfig
  60 from Caches import *
  61 from cpu2000 import *
  62
  63 parser = optparse.OptionParser()
  64 Options.addCommonOptions(parser)
  65 Options.addSEOptions(parser)
  66
  67 if '--ruby' in sys.argv:
  68     Ruby.define_options(parser)
  69
  70 (options, args) = parser.parse_args()
  71
  72 if args:
  73     print "Error: script doesn't take any positional arguments"
  74     sys.exit(1)
  75
  76 multiprocesses = []
  77 apps = []
  78
  79 if options.bench:
  80     apps = options.bench.split("-")
  81     if len(apps) != options.num_cpus:
  82         print "number of benchmarks not equal to set num_cpus!"
  83         sys.exit(1)
  84
  85     for app in apps:
  86         try:
  87             if buildEnv['TARGET_ISA'] == 'alpha':
  88                 exec("workload = %s('alpha', 'tru64', 'ref')" % app)
  89             else:
  90                 exec("workload = %s(buildEnv['TARGET_ISA'], 'linux', 'ref')" % app)
  91             multiprocesses.append(workload.makeLiveProcess())
  92         except:
  93             print >>sys.stderr, "Unable to find workload for %s: %s" % (buildEnv['TARGET_ISA'], app)
  94             sys.exit(1)
  95 elif options.cmd:
  96     process = LiveProcess()
  97     process.executable = options.cmd
  98     process.cmd = [options.cmd] + options.options.split()
  99     multiprocesses.append(process)
 100 else:
 101     print >> sys.stderr, "No workload specified. Exiting!\n"
 102     sys.exit(1)
 103
 104
 105 if options.input != "":
 106     process.input = options.input
 107 if options.output != "":
 108     process.output = options.output
 109 if options.errout != "":
 110     process.errout = options.errout
 111
 112
 113 # By default, set workload to path of user-specified binary
 114 workloads = options.cmd
 115 numThreads = 1
 116
 117 if options.cpu_type == "detailed" or options.cpu_type == "inorder":
 118     #check for SMT workload
 119     workloads = options.cmd.split(';')
 120     if len(workloads) > 1:
 121         process = []
 122         smt_idx = 0
 123         inputs = []
 124         outputs = []
 125         errouts = []
 126
 127         if options.input != "":
 128             inputs = options.input.split(';')
 129         if options.output != "":
 130             outputs = options.output.split(';')
 131         if options.errout != "":
 132             errouts = options.errout.split(';')
 133
 134         for wrkld in workloads:
 135             smt_process = LiveProcess()
 136             smt_process.executable = wrkld
 137             smt_process.cmd = wrkld + " " + options.options
 138             if inputs and inputs[smt_idx]:
 139                 smt_process.input = inputs[smt_idx]
 140             if outputs and outputs[smt_idx]:
 141                 smt_process.output = outputs[smt_idx]
 142             if errouts and errouts[smt_idx]:
 143                 smt_process.errout = errouts[smt_idx]
 144             process += [smt_process, ]
 145             smt_idx += 1
 146     numThreads = len(workloads)
 147
 148 (CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
 149 CPUClass.clock = '2GHz'
 150 CPUClass.numThreads = numThreads;
 151
 152 np = options.num_cpus
 153
 154 system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
 155                 physmem = SimpleMemory(range=AddrRange("512MB")),
 156                 membus = Bus(), mem_mode = test_mem_mode)
 157
 158 # Sanity check
 159 if options.fastmem and (options.caches or options.l2cache):
 160     fatal("You cannot use fastmem in combination with caches!")
 161
 162 for i in xrange(np):
 163     system.cpu[i].workload = multiprocesses[i]
 164
 165     if options.fastmem:
 166         system.cpu[0].fastmem = True
 167
 168     if options.checker:
 169         system.cpu[i].addCheckerCpu()
 170
 171 if options.ruby:
 172     if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
 173         print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
 174         sys.exit(1)
 175
 176     options.use_map = True
 177     Ruby.create_system(options, system)
 178     assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
 179
 180     for i in xrange(np):
 181         ruby_port = system.ruby._cpu_ruby_ports[i]
 182
 183         # Create the interrupt controller and connect its ports to Ruby
 184         system.cpu[i].createInterruptController()
 185         system.cpu[i].interrupts.pio = ruby_port.master
 186         system.cpu[i].interrupts.int_master = ruby_port.slave
 187         system.cpu[i].interrupts.int_slave = ruby_port.master
 188
 189         # Connect the cpu's cache ports to Ruby
 190         system.cpu[i].icache_port = ruby_port.slave
 191         system.cpu[i].dcache_port = ruby_port.slave
 192 else:
 193     system.system_port = system.membus.slave
 194     system.physmem.port = system.membus.master
 195     CacheConfig.config_cache(options, system)
 196
 197 root = Root(full_system = False, system = system)
 198 Simulation.run(options, root, system, FutureClass)