f2a26709e6ff12b28bde78808cb3677d144915d2
1 # Copyright (c) 2012 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2006-2008 The Regents of The University of Michigan
14 # All rights reserved.
16 # Redistribution and use in source and binary forms, with or without
17 # modification, are permitted provided that the following conditions are
18 # met: redistributions of source code must retain the above copyright
19 # notice, this list of conditions and the following disclaimer;
20 # redistributions in binary form must reproduce the above copyright
21 # notice, this list of conditions and the following disclaimer in the
22 # documentation and/or other materials provided with the distribution;
23 # neither the name of the copyright holders nor the names of its
24 # contributors may be used to endorse or promote products derived from
25 # this software without specific prior written permission.
27 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 # Authors: Steve Reinhardt
48 from os
.path
import join
as joinpath
51 from m5
.defines
import buildEnv
52 from m5
.objects
import *
53 from m5
.util
import addToPath
, fatal
55 addToPath('../common')
65 # Get paths we might need. It's expected this file is in m5/configs/example.
66 config_path
= os
.path
.dirname(os
.path
.abspath(__file__
))
67 config_root
= os
.path
.dirname(config_path
)
68 m5_root
= os
.path
.dirname(config_root
)
70 parser
= optparse
.OptionParser()
73 parser
.add_option("-c", "--cmd",
74 default
=joinpath(m5_root
, "tests/test-progs/hello/bin/%s/linux/hello" % \
75 buildEnv
['TARGET_ISA']),
76 help="The binary to run in syscall emulation mode.")
77 parser
.add_option("-o", "--options", default
="",
78 help='The options to pass to the binary, use " " around the entire string')
79 parser
.add_option("-i", "--input", default
="", help="Read stdin from a file.")
80 parser
.add_option("--output", default
="", help="Redirect stdout to a file.")
81 parser
.add_option("--errout", default
="", help="Redirect stderr to a file.")
83 execfile(os
.path
.join(config_root
, "common", "Options.py"))
85 if '--ruby' in sys
.argv
:
86 Ruby
.define_options(parser
)
88 (options
, args
) = parser
.parse_args()
91 print "Error: script doesn't take any positional arguments"
98 apps
= options
.bench
.split("-")
99 if len(apps
) != options
.num_cpus
:
100 print "number of benchmarks not equal to set num_cpus!"
105 if buildEnv
['TARGET_ISA'] == 'alpha':
106 exec("workload = %s('alpha', 'tru64', 'ref')" % app
)
108 exec("workload = %s(buildEnv['TARGET_ISA'], 'linux', 'ref')" % app
)
109 multiprocesses
.append(workload
.makeLiveProcess())
111 print >>sys
.stderr
, "Unable to find workload for %s: %s" % (buildEnv
['TARGET_ISA'], app
)
114 process
= LiveProcess()
115 process
.executable
= options
.cmd
116 process
.cmd
= [options
.cmd
] + options
.options
.split()
117 multiprocesses
.append(process
)
120 if options
.input != "":
121 process
.input = options
.input
122 if options
.output
!= "":
123 process
.output
= options
.output
124 if options
.errout
!= "":
125 process
.errout
= options
.errout
128 # By default, set workload to path of user-specified binary
129 workloads
= options
.cmd
132 if options
.cpu_type
== "detailed" or options
.cpu_type
== "inorder":
133 #check for SMT workload
134 workloads
= options
.cmd
.split(';')
135 if len(workloads
) > 1:
142 if options
.input != "":
143 inputs
= options
.input.split(';')
144 if options
.output
!= "":
145 outputs
= options
.output
.split(';')
146 if options
.errout
!= "":
147 errouts
= options
.errout
.split(';')
149 for wrkld
in workloads
:
150 smt_process
= LiveProcess()
151 smt_process
.executable
= wrkld
152 smt_process
.cmd
= wrkld
+ " " + options
.options
153 if inputs
and inputs
[smt_idx
]:
154 smt_process
.input = inputs
[smt_idx
]
155 if outputs
and outputs
[smt_idx
]:
156 smt_process
.output
= outputs
[smt_idx
]
157 if errouts
and errouts
[smt_idx
]:
158 smt_process
.errout
= errouts
[smt_idx
]
159 process
+= [smt_process
, ]
161 numThreads
= len(workloads
)
164 if not (options
.cpu_type
== "detailed" or options
.cpu_type
== "timing"):
165 print >> sys
.stderr
, "Ruby requires TimingSimpleCPU or O3CPU!!"
168 (CPUClass
, test_mem_mode
, FutureClass
) = Simulation
.setCPUClass(options
)
169 CPUClass
.clock
= '2GHz'
170 CPUClass
.numThreads
= numThreads
;
172 np
= options
.num_cpus
174 system
= System(cpu
= [CPUClass(cpu_id
=i
) for i
in xrange(np
)],
175 physmem
= PhysicalMemory(range=AddrRange("512MB")),
176 membus
= Bus(), mem_mode
= test_mem_mode
)
179 options
.use_map
= True
180 Ruby
.create_system(options
, system
)
181 assert(options
.num_cpus
== len(system
.ruby
._cpu
_ruby
_ports
))
183 system
.system_port
= system
.membus
.slave
184 system
.physmem
.port
= system
.membus
.master
185 CacheConfig
.config_cache(options
, system
)
188 system
.cpu
[i
].workload
= multiprocesses
[i
]
191 system
.cpu
[i
].icache_port
= system
.ruby
._cpu
_ruby
_ports
[i
].slave
192 system
.cpu
[i
].dcache_port
= system
.ruby
._cpu
_ruby
_ports
[i
].slave
195 system
.cpu
[0].physmem_port
= system
.physmem
.port
197 root
= Root(full_system
= False, system
= system
)
199 Simulation
.run(options
, root
, system
, FutureClass
)