configs/example/se.py

   1 # Copyright (c) 2012-2013 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
   6 # property including but not limited to intellectual property relating
   7 # to a hardware implementation of the functionality of the software
   8 # licensed hereunder.  You may use the software subject to the license
   9 # terms below provided that you ensure that this notice is replicated
  10 # unmodified and in its entirety in all distributions of the software,
  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Copyright (c) 2006-2008 The Regents of The University of Michigan
  14 # All rights reserved.
  15 #
  16 # Redistribution and use in source and binary forms, with or without
  17 # modification, are permitted provided that the following conditions are
  18 # met: redistributions of source code must retain the above copyright
  19 # notice, this list of conditions and the following disclaimer;
  20 # redistributions in binary form must reproduce the above copyright
  21 # notice, this list of conditions and the following disclaimer in the
  22 # documentation and/or other materials provided with the distribution;
  23 # neither the name of the copyright holders nor the names of its
  24 # contributors may be used to endorse or promote products derived from
  25 # this software without specific prior written permission.
  26 #
  27 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  30 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  32 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  33 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  34 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  35 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  36 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  37 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38 #
  39 # Authors: Steve Reinhardt
  40
  41 # Simple test script
  42 #
  43 # "m5 test.py"
  44
  45 import optparse
  46 import sys
  47 import os
  48
  49 import m5
  50 from m5.defines import buildEnv
  51 from m5.objects import *
  52 from m5.util import addToPath, fatal
  53
  54 addToPath('../common')
  55 addToPath('../ruby')
  56
  57 import Options
  58 import Ruby
  59 import Simulation
  60 import CacheConfig
  61 import MemConfig
  62 from Caches import *
  63 from cpu2000 import *
  64
  65 def get_processes(options):
  66     """Interprets provided options and returns a list of processes"""
  67
  68     multiprocesses = []
  69     inputs = []
  70     outputs = []
  71     errouts = []
  72     pargs = []
  73
  74     workloads = options.cmd.split(';')
  75     if options.input != "":
  76         inputs = options.input.split(';')
  77     if options.output != "":
  78         outputs = options.output.split(';')
  79     if options.errout != "":
  80         errouts = options.errout.split(';')
  81     if options.options != "":
  82         pargs = options.options.split(';')
  83
  84     idx = 0
  85     for wrkld in workloads:
  86         process = LiveProcess()
  87         process.executable = wrkld
  88         process.cwd = os.getcwd()
  89
  90         if len(pargs) > idx:
  91             process.cmd = [wrkld] + pargs[idx].split()
  92         else:
  93             process.cmd = [wrkld]
  94
  95         if len(inputs) > idx:
  96             process.input = inputs[idx]
  97         if len(outputs) > idx:
  98             process.output = outputs[idx]
  99         if len(errouts) > idx:
 100             process.errout = errouts[idx]
 101
 102         multiprocesses.append(process)
 103         idx += 1
 104
 105     if options.smt:
 106         assert(options.cpu_type == "detailed" or options.cpu_type == "inorder")
 107         return multiprocesses, idx
 108     else:
 109         return multiprocesses, 1
 110
 111
 112 parser = optparse.OptionParser()
 113 Options.addCommonOptions(parser)
 114 Options.addSEOptions(parser)
 115
 116 if '--ruby' in sys.argv:
 117     Ruby.define_options(parser)
 118
 119 (options, args) = parser.parse_args()
 120
 121 if args:
 122     print "Error: script doesn't take any positional arguments"
 123     sys.exit(1)
 124
 125 multiprocesses = []
 126 numThreads = 1
 127
 128 if options.bench:
 129     apps = options.bench.split("-")
 130     if len(apps) != options.num_cpus:
 131         print "number of benchmarks not equal to set num_cpus!"
 132         sys.exit(1)
 133
 134     for app in apps:
 135         try:
 136             if buildEnv['TARGET_ISA'] == 'alpha':
 137                 exec("workload = %s('alpha', 'tru64', '%s')" % (
 138                         app, options.spec_input))
 139             elif buildEnv['TARGET_ISA'] == 'arm':
 140                 exec("workload = %s('arm_%s', 'linux', '%s')" % (
 141                         app, options.arm_iset, options.spec_input))
 142             else:
 143                 exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % (
 144                         app, options.spec_input))
 145             multiprocesses.append(workload.makeLiveProcess())
 146         except:
 147             print >>sys.stderr, "Unable to find workload for %s: %s" % (
 148                     buildEnv['TARGET_ISA'], app)
 149             sys.exit(1)
 150 elif options.cmd:
 151     multiprocesses, numThreads = get_processes(options)
 152 else:
 153     print >> sys.stderr, "No workload specified. Exiting!\n"
 154     sys.exit(1)
 155
 156
 157 (CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
 158 CPUClass.numThreads = numThreads
 159
 160 # Check -- do not allow SMT with multiple CPUs
 161 if options.smt and options.num_cpus > 1:
 162     fatal("You cannot use SMT with multiple CPUs!")
 163
 164 np = options.num_cpus
 165 system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
 166                 mem_mode = test_mem_mode,
 167                 mem_ranges = [AddrRange(options.mem_size)],
 168                 cache_line_size = options.cacheline_size)
 169
 170 # Create a top-level voltage domain
 171 system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
 172
 173 # Create a source clock for the system and set the clock period
 174 system.clk_domain = SrcClockDomain(clock =  options.sys_clock,
 175                                    voltage_domain = system.voltage_domain)
 176
 177 # Create a CPU voltage domain
 178 system.cpu_voltage_domain = VoltageDomain()
 179
 180 # Create a separate clock domain for the CPUs
 181 system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
 182                                        voltage_domain =
 183                                        system.cpu_voltage_domain)
 184
 185 # All cpus belong to a common cpu_clk_domain, therefore running at a common
 186 # frequency.
 187 for cpu in system.cpu:
 188     cpu.clk_domain = system.cpu_clk_domain
 189
 190 # Sanity check
 191 if options.fastmem:
 192     if CPUClass != AtomicSimpleCPU:
 193         fatal("Fastmem can only be used with atomic CPU!")
 194     if (options.caches or options.l2cache):
 195         fatal("You cannot use fastmem in combination with caches!")
 196
 197 if options.simpoint_profile:
 198     if not options.fastmem:
 199         # Atomic CPU checked with fastmem option already
 200         fatal("SimPoint generation should be done with atomic cpu and fastmem")
 201     if np > 1:
 202         fatal("SimPoint generation not supported with more than one CPUs")
 203
 204 for i in xrange(np):
 205     if options.smt:
 206         system.cpu[i].workload = multiprocesses
 207     elif len(multiprocesses) == 1:
 208         system.cpu[i].workload = multiprocesses[0]
 209     else:
 210         system.cpu[i].workload = multiprocesses[i]
 211
 212     if options.fastmem:
 213         system.cpu[i].fastmem = True
 214
 215     if options.simpoint_profile:
 216         system.cpu[i].addSimPointProbe(options.simpoint_interval)
 217
 218     if options.checker:
 219         system.cpu[i].addCheckerCpu()
 220
 221     system.cpu[i].createThreads()
 222
 223 if options.ruby:
 224     if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
 225         print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
 226         sys.exit(1)
 227
 228     options.use_map = True
 229     Ruby.create_system(options, False, system)
 230     assert(options.num_cpus == len(system.ruby._cpu_ports))
 231
 232     system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
 233                                         voltage_domain = system.voltage_domain)
 234     for i in xrange(np):
 235         ruby_port = system.ruby._cpu_ports[i]
 236
 237         # Create the interrupt controller and connect its ports to Ruby
 238         # Note that the interrupt controller is always present but only
 239         # in x86 does it have message ports that need to be connected
 240         system.cpu[i].createInterruptController()
 241
 242         # Connect the cpu's cache ports to Ruby
 243         system.cpu[i].icache_port = ruby_port.slave
 244         system.cpu[i].dcache_port = ruby_port.slave
 245         if buildEnv['TARGET_ISA'] == 'x86':
 246             system.cpu[i].interrupts.pio = ruby_port.master
 247             system.cpu[i].interrupts.int_master = ruby_port.slave
 248             system.cpu[i].interrupts.int_slave = ruby_port.master
 249             system.cpu[i].itb.walker.port = ruby_port.slave
 250             system.cpu[i].dtb.walker.port = ruby_port.slave
 251 else:
 252     MemClass = Simulation.setMemClass(options)
 253     system.membus = CoherentXBar()
 254     system.system_port = system.membus.slave
 255     CacheConfig.config_cache(options, system)
 256     MemConfig.config_mem(options, system)
 257
 258 root = Root(full_system = False, system = system)
 259 Simulation.run(options, root, system, FutureClass)