1 # Copyright (c) 2012-2013 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2006-2008 The Regents of The University of Michigan
14 # All rights reserved.
16 # Redistribution and use in source and binary forms, with or without
17 # modification, are permitted provided that the following conditions are
18 # met: redistributions of source code must retain the above copyright
19 # notice, this list of conditions and the following disclaimer;
20 # redistributions in binary form must reproduce the above copyright
21 # notice, this list of conditions and the following disclaimer in the
22 # documentation and/or other materials provided with the distribution;
23 # neither the name of the copyright holders nor the names of its
24 # contributors may be used to endorse or promote products derived from
25 # this software without specific prior written permission.
27 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 # Authors: Steve Reinhardt
50 from m5
.defines
import buildEnv
51 from m5
.objects
import *
52 from m5
.util
import addToPath
, fatal
54 addToPath('../common')
65 # Check if KVM support has been enabled, we might need to do VM
66 # configuration if that's the case.
67 have_kvm_support
= 'BaseKvmCPU' in globals()
68 def is_kvm_cpu(cpu_class
):
69 return have_kvm_support
and cpu_class
!= None and \
70 issubclass(cpu_class
, BaseKvmCPU
)
72 def get_processes(options
):
73 """Interprets provided options and returns a list of processes"""
81 workloads
= options
.cmd
.split(';')
82 if options
.input != "":
83 inputs
= options
.input.split(';')
84 if options
.output
!= "":
85 outputs
= options
.output
.split(';')
86 if options
.errout
!= "":
87 errouts
= options
.errout
.split(';')
88 if options
.options
!= "":
89 pargs
= options
.options
.split(';')
92 for wrkld
in workloads
:
93 process
= LiveProcess()
94 process
.executable
= wrkld
95 process
.cwd
= os
.getcwd()
98 process
.cmd
= [wrkld
] + pargs
[idx
].split()
100 process
.cmd
= [wrkld
]
102 if len(inputs
) > idx
:
103 process
.input = inputs
[idx
]
104 if len(outputs
) > idx
:
105 process
.output
= outputs
[idx
]
106 if len(errouts
) > idx
:
107 process
.errout
= errouts
[idx
]
109 multiprocesses
.append(process
)
113 assert(options
.cpu_type
== "detailed")
114 return multiprocesses
, idx
116 return multiprocesses
, 1
119 parser
= optparse
.OptionParser()
120 Options
.addCommonOptions(parser
)
121 Options
.addSEOptions(parser
)
123 if '--ruby' in sys
.argv
:
124 Ruby
.define_options(parser
)
126 (options
, args
) = parser
.parse_args()
129 print "Error: script doesn't take any positional arguments"
136 apps
= options
.bench
.split("-")
137 if len(apps
) != options
.num_cpus
:
138 print "number of benchmarks not equal to set num_cpus!"
143 if buildEnv
['TARGET_ISA'] == 'alpha':
144 exec("workload = %s('alpha', 'tru64', '%s')" % (
145 app
, options
.spec_input
))
146 elif buildEnv
['TARGET_ISA'] == 'arm':
147 exec("workload = %s('arm_%s', 'linux', '%s')" % (
148 app
, options
.arm_iset
, options
.spec_input
))
150 exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % (
151 app
, options
.spec_input
))
152 multiprocesses
.append(workload
.makeLiveProcess())
154 print >>sys
.stderr
, "Unable to find workload for %s: %s" % (
155 buildEnv
['TARGET_ISA'], app
)
158 multiprocesses
, numThreads
= get_processes(options
)
160 print >> sys
.stderr
, "No workload specified. Exiting!\n"
164 (CPUClass
, test_mem_mode
, FutureClass
) = Simulation
.setCPUClass(options
)
165 CPUClass
.numThreads
= numThreads
167 # Check -- do not allow SMT with multiple CPUs
168 if options
.smt
and options
.num_cpus
> 1:
169 fatal("You cannot use SMT with multiple CPUs!")
171 np
= options
.num_cpus
172 system
= System(cpu
= [CPUClass(cpu_id
=i
) for i
in xrange(np
)],
173 mem_mode
= test_mem_mode
,
174 mem_ranges
= [AddrRange(options
.mem_size
)],
175 cache_line_size
= options
.cacheline_size
)
177 # Create a top-level voltage domain
178 system
.voltage_domain
= VoltageDomain(voltage
= options
.sys_voltage
)
180 # Create a source clock for the system and set the clock period
181 system
.clk_domain
= SrcClockDomain(clock
= options
.sys_clock
,
182 voltage_domain
= system
.voltage_domain
)
184 # Create a CPU voltage domain
185 system
.cpu_voltage_domain
= VoltageDomain()
187 # Create a separate clock domain for the CPUs
188 system
.cpu_clk_domain
= SrcClockDomain(clock
= options
.cpu_clock
,
190 system
.cpu_voltage_domain
)
192 # All cpus belong to a common cpu_clk_domain, therefore running at a common
194 for cpu
in system
.cpu
:
195 cpu
.clk_domain
= system
.cpu_clk_domain
197 if is_kvm_cpu(CPUClass
) or is_kvm_cpu(FutureClass
):
198 if buildEnv
['TARGET_ISA'] == 'x86':
200 for process
in multiprocesses
:
201 process
.useArchPT
= True
202 process
.kvmInSE
= True
204 fatal("KvmCPU can only be used in SE mode with x86")
208 if CPUClass
!= AtomicSimpleCPU
:
209 fatal("Fastmem can only be used with atomic CPU!")
210 if (options
.caches
or options
.l2cache
):
211 fatal("You cannot use fastmem in combination with caches!")
213 if options
.simpoint_profile
:
214 if not options
.fastmem
:
215 # Atomic CPU checked with fastmem option already
216 fatal("SimPoint generation should be done with atomic cpu and fastmem")
218 fatal("SimPoint generation not supported with more than one CPUs")
222 system
.cpu
[i
].workload
= multiprocesses
223 elif len(multiprocesses
) == 1:
224 system
.cpu
[i
].workload
= multiprocesses
[0]
226 system
.cpu
[i
].workload
= multiprocesses
[i
]
229 system
.cpu
[i
].fastmem
= True
231 if options
.simpoint_profile
:
232 system
.cpu
[i
].addSimPointProbe(options
.simpoint_interval
)
235 system
.cpu
[i
].addCheckerCpu()
237 system
.cpu
[i
].createThreads()
240 if not (options
.cpu_type
== "detailed" or options
.cpu_type
== "timing"):
241 print >> sys
.stderr
, "Ruby requires TimingSimpleCPU or O3CPU!!"
244 Ruby
.create_system(options
, False, system
)
245 assert(options
.num_cpus
== len(system
.ruby
._cpu
_ports
))
247 system
.ruby
.clk_domain
= SrcClockDomain(clock
= options
.ruby_clock
,
248 voltage_domain
= system
.voltage_domain
)
250 ruby_port
= system
.ruby
._cpu
_ports
[i
]
252 # Create the interrupt controller and connect its ports to Ruby
253 # Note that the interrupt controller is always present but only
254 # in x86 does it have message ports that need to be connected
255 system
.cpu
[i
].createInterruptController()
257 # Connect the cpu's cache ports to Ruby
258 system
.cpu
[i
].icache_port
= ruby_port
.slave
259 system
.cpu
[i
].dcache_port
= ruby_port
.slave
260 if buildEnv
['TARGET_ISA'] == 'x86':
261 system
.cpu
[i
].interrupts
.pio
= ruby_port
.master
262 system
.cpu
[i
].interrupts
.int_master
= ruby_port
.slave
263 system
.cpu
[i
].interrupts
.int_slave
= ruby_port
.master
264 system
.cpu
[i
].itb
.walker
.port
= ruby_port
.slave
265 system
.cpu
[i
].dtb
.walker
.port
= ruby_port
.slave
267 MemClass
= Simulation
.setMemClass(options
)
268 system
.membus
= CoherentXBar()
269 system
.system_port
= system
.membus
.slave
270 CacheConfig
.config_cache(options
, system
)
271 MemConfig
.config_mem(options
, system
)
273 root
= Root(full_system
= False, system
= system
)
274 Simulation
.run(options
, root
, system
, FutureClass
)