configs/example/se.py

   1 # Copyright (c) 2012-2013 ARM Limited
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  13 # Copyright (c) 2006-2008 The Regents of The University of Michigan
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  38 #
  39 # Authors: Steve Reinhardt
  40
  41 # Simple test script
  42 #
  43 # "m5 test.py"
  44
  45 from __future__ import print_function
  46 from __future__ import absolute_import
  47
  48 import optparse
  49 import sys
  50 import os
  51
  52 import m5
  53 from m5.defines import buildEnv
  54 from m5.objects import *
  55 from m5.util import addToPath, fatal, warn
  56
  57 addToPath('../')
  58
  59 from ruby import Ruby
  60
  61 from common import Options
  62 from common import Simulation
  63 from common import CacheConfig
  64 from common import CpuConfig
  65 from common import ObjectList
  66 from common import MemConfig
  67 from common.FileSystemConfig import config_filesystem
  68 from common.Caches import *
  69 from common.cpu2000 import *
  70
  71 def get_processes(options):
  72     """Interprets provided options and returns a list of processes"""
  73
  74     multiprocesses = []
  75     inputs = []
  76     outputs = []
  77     errouts = []
  78     pargs = []
  79
  80     workloads = options.cmd.split(';')
  81     if options.input != "":
  82         inputs = options.input.split(';')
  83     if options.output != "":
  84         outputs = options.output.split(';')
  85     if options.errout != "":
  86         errouts = options.errout.split(';')
  87     if options.options != "":
  88         pargs = options.options.split(';')
  89
  90     idx = 0
  91     for wrkld in workloads:
  92         process = Process(pid = 100 + idx)
  93         process.executable = wrkld
  94         process.cwd = os.getcwd()
  95
  96         if options.env:
  97             with open(options.env, 'r') as f:
  98                 process.env = [line.rstrip() for line in f]
  99
 100         if len(pargs) > idx:
 101             process.cmd = [wrkld] + pargs[idx].split()
 102         else:
 103             process.cmd = [wrkld]
 104
 105         if len(inputs) > idx:
 106             process.input = inputs[idx]
 107         if len(outputs) > idx:
 108             process.output = outputs[idx]
 109         if len(errouts) > idx:
 110             process.errout = errouts[idx]
 111
 112         multiprocesses.append(process)
 113         idx += 1
 114
 115     if options.smt:
 116         assert(options.cpu_type == "DerivO3CPU")
 117         return multiprocesses, idx
 118     else:
 119         return multiprocesses, 1
 120
 121
 122 parser = optparse.OptionParser()
 123 Options.addCommonOptions(parser)
 124 Options.addSEOptions(parser)
 125
 126 if '--ruby' in sys.argv:
 127     Ruby.define_options(parser)
 128
 129 (options, args) = parser.parse_args()
 130
 131 if args:
 132     print("Error: script doesn't take any positional arguments")
 133     sys.exit(1)
 134
 135 multiprocesses = []
 136 numThreads = 1
 137
 138 if options.bench:
 139     apps = options.bench.split("-")
 140     if len(apps) != options.num_cpus:
 141         print("number of benchmarks not equal to set num_cpus!")
 142         sys.exit(1)
 143
 144     for app in apps:
 145         try:
 146             if buildEnv['TARGET_ISA'] == 'arm':
 147                 exec("workload = %s('arm_%s', 'linux', '%s')" % (
 148                         app, options.arm_iset, options.spec_input))
 149             else:
 150                 exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % (
 151                         app, options.spec_input))
 152             multiprocesses.append(workload.makeProcess())
 153         except:
 154             print("Unable to find workload for %s: %s" %
 155                   (buildEnv['TARGET_ISA'], app),
 156                   file=sys.stderr)
 157             sys.exit(1)
 158 elif options.cmd:
 159     multiprocesses, numThreads = get_processes(options)
 160 else:
 161     print("No workload specified. Exiting!\n", file=sys.stderr)
 162     sys.exit(1)
 163
 164
 165 (CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
 166 CPUClass.numThreads = numThreads
 167
 168 # Check -- do not allow SMT with multiple CPUs
 169 if options.smt and options.num_cpus > 1:
 170     fatal("You cannot use SMT with multiple CPUs!")
 171
 172 np = options.num_cpus
 173 system = System(cpu = [CPUClass(cpu_id=i) for i in range(np)],
 174                 mem_mode = test_mem_mode,
 175                 mem_ranges = [AddrRange(options.mem_size)],
 176                 cache_line_size = options.cacheline_size)
 177
 178 if numThreads > 1:
 179     system.multi_thread = True
 180
 181 # Create a top-level voltage domain
 182 system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
 183
 184 # Create a source clock for the system and set the clock period
 185 system.clk_domain = SrcClockDomain(clock =  options.sys_clock,
 186                                    voltage_domain = system.voltage_domain)
 187
 188 # Create a CPU voltage domain
 189 system.cpu_voltage_domain = VoltageDomain()
 190
 191 # Create a separate clock domain for the CPUs
 192 system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
 193                                        voltage_domain =
 194                                        system.cpu_voltage_domain)
 195
 196 # If elastic tracing is enabled, then configure the cpu and attach the elastic
 197 # trace probe
 198 if options.elastic_trace_en:
 199     CpuConfig.config_etrace(CPUClass, system.cpu, options)
 200
 201 # All cpus belong to a common cpu_clk_domain, therefore running at a common
 202 # frequency.
 203 for cpu in system.cpu:
 204     cpu.clk_domain = system.cpu_clk_domain
 205
 206 if ObjectList.is_kvm_cpu(CPUClass) or ObjectList.is_kvm_cpu(FutureClass):
 207     if buildEnv['TARGET_ISA'] == 'x86':
 208         system.kvm_vm = KvmVM()
 209         for process in multiprocesses:
 210             process.useArchPT = True
 211             process.kvmInSE = True
 212     else:
 213         fatal("KvmCPU can only be used in SE mode with x86")
 214
 215 # Sanity check
 216 if options.simpoint_profile:
 217     if not ObjectList.is_noncaching_cpu(CPUClass):
 218         fatal("SimPoint/BPProbe should be done with an atomic cpu")
 219     if np > 1:
 220         fatal("SimPoint generation not supported with more than one CPUs")
 221
 222 for i in range(np):
 223     if options.smt:
 224         system.cpu[i].workload = multiprocesses
 225     elif len(multiprocesses) == 1:
 226         system.cpu[i].workload = multiprocesses[0]
 227     else:
 228         system.cpu[i].workload = multiprocesses[i]
 229
 230     if options.simpoint_profile:
 231         system.cpu[i].addSimPointProbe(options.simpoint_interval)
 232
 233     if options.checker:
 234         system.cpu[i].addCheckerCpu()
 235
 236     if options.bp_type:
 237         bpClass = ObjectList.bp_list.get(options.bp_type)
 238         system.cpu[i].branchPred = bpClass()
 239
 240     if options.indirect_bp_type:
 241         indirectBPClass = \
 242             ObjectList.indirect_bp_list.get(options.indirect_bp_type)
 243         system.cpu[i].branchPred.indirectBranchPred = indirectBPClass()
 244
 245     system.cpu[i].createThreads()
 246
 247 if options.ruby:
 248     Ruby.create_system(options, False, system)
 249     assert(options.num_cpus == len(system.ruby._cpu_ports))
 250
 251     system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
 252                                         voltage_domain = system.voltage_domain)
 253     for i in range(np):
 254         ruby_port = system.ruby._cpu_ports[i]
 255
 256         # Create the interrupt controller and connect its ports to Ruby
 257         # Note that the interrupt controller is always present but only
 258         # in x86 does it have message ports that need to be connected
 259         system.cpu[i].createInterruptController()
 260
 261         # Connect the cpu's cache ports to Ruby
 262         system.cpu[i].icache_port = ruby_port.slave
 263         system.cpu[i].dcache_port = ruby_port.slave
 264         if buildEnv['TARGET_ISA'] == 'x86':
 265             system.cpu[i].interrupts[0].pio = ruby_port.master
 266             system.cpu[i].interrupts[0].int_master = ruby_port.slave
 267             system.cpu[i].interrupts[0].int_slave = ruby_port.master
 268             system.cpu[i].itb.walker.port = ruby_port.slave
 269             system.cpu[i].dtb.walker.port = ruby_port.slave
 270 else:
 271     MemClass = Simulation.setMemClass(options)
 272     system.membus = SystemXBar()
 273     system.system_port = system.membus.slave
 274     CacheConfig.config_cache(options, system)
 275     MemConfig.config_mem(options, system)
 276     config_filesystem(system, options)
 277
 278 root = Root(full_system = False, system = system)
 279 Simulation.run(options, root, system, FutureClass)