1 # Copyright (c) 2012-2013 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2006-2008 The Regents of The University of Michigan
14 # All rights reserved.
16 # Redistribution and use in source and binary forms, with or without
17 # modification, are permitted provided that the following conditions are
18 # met: redistributions of source code must retain the above copyright
19 # notice, this list of conditions and the following disclaimer;
20 # redistributions in binary form must reproduce the above copyright
21 # notice, this list of conditions and the following disclaimer in the
22 # documentation and/or other materials provided with the distribution;
23 # neither the name of the copyright holders nor the names of its
24 # contributors may be used to endorse or promote products derived from
25 # this software without specific prior written permission.
27 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 from __future__
import print_function
44 from __future__
import absolute_import
51 from m5
.defines
import buildEnv
52 from m5
.objects
import *
53 from m5
.params
import NULL
54 from m5
.util
import addToPath
, fatal
, warn
60 from common
import Options
61 from common
import Simulation
62 from common
import CacheConfig
63 from common
import CpuConfig
64 from common
import ObjectList
65 from common
import MemConfig
66 from common
.FileSystemConfig
import config_filesystem
67 from common
.Caches
import *
68 from common
.cpu2000
import *
70 def get_processes(options
):
71 """Interprets provided options and returns a list of processes"""
79 workloads
= options
.cmd
.split(';')
80 if options
.input != "":
81 inputs
= options
.input.split(';')
82 if options
.output
!= "":
83 outputs
= options
.output
.split(';')
84 if options
.errout
!= "":
85 errouts
= options
.errout
.split(';')
86 if options
.options
!= "":
87 pargs
= options
.options
.split(';')
90 for wrkld
in workloads
:
91 process
= Process(pid
= 100 + idx
)
92 process
.executable
= wrkld
93 process
.cwd
= os
.getcwd()
96 with
open(options
.env
, 'r') as f
:
97 process
.env
= [line
.rstrip() for line
in f
]
100 process
.cmd
= [wrkld
] + pargs
[idx
].split()
102 process
.cmd
= [wrkld
]
104 if len(inputs
) > idx
:
105 process
.input = inputs
[idx
]
106 if len(outputs
) > idx
:
107 process
.output
= outputs
[idx
]
108 if len(errouts
) > idx
:
109 process
.errout
= errouts
[idx
]
111 multiprocesses
.append(process
)
115 assert(options
.cpu_type
== "DerivO3CPU")
116 return multiprocesses
, idx
118 return multiprocesses
, 1
121 parser
= optparse
.OptionParser()
122 Options
.addCommonOptions(parser
)
123 Options
.addSEOptions(parser
)
125 if '--ruby' in sys
.argv
:
126 Ruby
.define_options(parser
)
128 (options
, args
) = parser
.parse_args()
131 print("Error: script doesn't take any positional arguments")
138 apps
= options
.bench
.split("-")
139 if len(apps
) != options
.num_cpus
:
140 print("number of benchmarks not equal to set num_cpus!")
145 if buildEnv
['TARGET_ISA'] == 'arm':
146 exec("workload = %s('arm_%s', 'linux', '%s')" % (
147 app
, options
.arm_iset
, options
.spec_input
))
149 exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % (
150 app
, options
.spec_input
))
151 multiprocesses
.append(workload
.makeProcess())
153 print("Unable to find workload for %s: %s" %
154 (buildEnv
['TARGET_ISA'], app
),
158 multiprocesses
, numThreads
= get_processes(options
)
160 print("No workload specified. Exiting!\n", file=sys
.stderr
)
164 (CPUClass
, test_mem_mode
, FutureClass
) = Simulation
.setCPUClass(options
)
165 CPUClass
.numThreads
= numThreads
167 # Check -- do not allow SMT with multiple CPUs
168 if options
.smt
and options
.num_cpus
> 1:
169 fatal("You cannot use SMT with multiple CPUs!")
171 np
= options
.num_cpus
172 system
= System(cpu
= [CPUClass(cpu_id
=i
) for i
in range(np
)],
173 mem_mode
= test_mem_mode
,
174 mem_ranges
= [AddrRange(options
.mem_size
)],
175 cache_line_size
= options
.cacheline_size
,
179 system
.multi_thread
= True
181 # Create a top-level voltage domain
182 system
.voltage_domain
= VoltageDomain(voltage
= options
.sys_voltage
)
184 # Create a source clock for the system and set the clock period
185 system
.clk_domain
= SrcClockDomain(clock
= options
.sys_clock
,
186 voltage_domain
= system
.voltage_domain
)
188 # Create a CPU voltage domain
189 system
.cpu_voltage_domain
= VoltageDomain()
191 # Create a separate clock domain for the CPUs
192 system
.cpu_clk_domain
= SrcClockDomain(clock
= options
.cpu_clock
,
194 system
.cpu_voltage_domain
)
196 # If elastic tracing is enabled, then configure the cpu and attach the elastic
198 if options
.elastic_trace_en
:
199 CpuConfig
.config_etrace(CPUClass
, system
.cpu
, options
)
201 # All cpus belong to a common cpu_clk_domain, therefore running at a common
203 for cpu
in system
.cpu
:
204 cpu
.clk_domain
= system
.cpu_clk_domain
206 if ObjectList
.is_kvm_cpu(CPUClass
) or ObjectList
.is_kvm_cpu(FutureClass
):
207 if buildEnv
['TARGET_ISA'] == 'x86':
208 system
.kvm_vm
= KvmVM()
209 for process
in multiprocesses
:
210 process
.useArchPT
= True
211 process
.kvmInSE
= True
213 fatal("KvmCPU can only be used in SE mode with x86")
216 if options
.simpoint_profile
:
217 if not ObjectList
.is_noncaching_cpu(CPUClass
):
218 fatal("SimPoint/BPProbe should be done with an atomic cpu")
220 fatal("SimPoint generation not supported with more than one CPUs")
224 system
.cpu
[i
].workload
= multiprocesses
225 elif len(multiprocesses
) == 1:
226 system
.cpu
[i
].workload
= multiprocesses
[0]
228 system
.cpu
[i
].workload
= multiprocesses
[i
]
230 if options
.simpoint_profile
:
231 system
.cpu
[i
].addSimPointProbe(options
.simpoint_interval
)
234 system
.cpu
[i
].addCheckerCpu()
237 bpClass
= ObjectList
.bp_list
.get(options
.bp_type
)
238 system
.cpu
[i
].branchPred
= bpClass()
240 if options
.indirect_bp_type
:
242 ObjectList
.indirect_bp_list
.get(options
.indirect_bp_type
)
243 system
.cpu
[i
].branchPred
.indirectBranchPred
= indirectBPClass()
245 system
.cpu
[i
].createThreads()
248 Ruby
.create_system(options
, False, system
)
249 assert(options
.num_cpus
== len(system
.ruby
._cpu
_ports
))
251 system
.ruby
.clk_domain
= SrcClockDomain(clock
= options
.ruby_clock
,
252 voltage_domain
= system
.voltage_domain
)
254 ruby_port
= system
.ruby
._cpu
_ports
[i
]
256 # Create the interrupt controller and connect its ports to Ruby
257 # Note that the interrupt controller is always present but only
258 # in x86 does it have message ports that need to be connected
259 system
.cpu
[i
].createInterruptController()
261 # Connect the cpu's cache ports to Ruby
262 system
.cpu
[i
].icache_port
= ruby_port
.slave
263 system
.cpu
[i
].dcache_port
= ruby_port
.slave
264 if buildEnv
['TARGET_ISA'] == 'x86':
265 system
.cpu
[i
].interrupts
[0].pio
= ruby_port
.master
266 system
.cpu
[i
].interrupts
[0].int_master
= ruby_port
.slave
267 system
.cpu
[i
].interrupts
[0].int_slave
= ruby_port
.master
268 system
.cpu
[i
].itb
.walker
.port
= ruby_port
.slave
269 system
.cpu
[i
].dtb
.walker
.port
= ruby_port
.slave
271 MemClass
= Simulation
.setMemClass(options
)
272 system
.membus
= SystemXBar()
273 system
.system_port
= system
.membus
.slave
274 CacheConfig
.config_cache(options
, system
)
275 MemConfig
.config_mem(options
, system
)
276 config_filesystem(system
, options
)
278 root
= Root(full_system
= False, system
= system
)
279 Simulation
.run(options
, root
, system
, FutureClass
)