1 # Copyright (c) 2012 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2006-2008 The Regents of The University of Michigan
14 # All rights reserved.
16 # Redistribution and use in source and binary forms, with or without
17 # modification, are permitted provided that the following conditions are
18 # met: redistributions of source code must retain the above copyright
19 # notice, this list of conditions and the following disclaimer;
20 # redistributions in binary form must reproduce the above copyright
21 # notice, this list of conditions and the following disclaimer in the
22 # documentation and/or other materials provided with the distribution;
23 # neither the name of the copyright holders nor the names of its
24 # contributors may be used to endorse or promote products derived from
25 # this software without specific prior written permission.
27 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 # Authors: Steve Reinhardt
49 from m5
.defines
import buildEnv
50 from m5
.objects
import *
51 from m5
.util
import addToPath
, fatal
53 addToPath('../common')
55 addToPath('../topologies')
64 def get_processes(options
):
65 """Interprets provided options and returns a list of processes"""
73 workloads
= options
.cmd
.split(';')
74 if options
.input != "":
75 inputs
= options
.input.split(';')
76 if options
.output
!= "":
77 outputs
= options
.output
.split(';')
78 if options
.errout
!= "":
79 errouts
= options
.errout
.split(';')
80 if options
.options
!= "":
81 pargs
= options
.options
.split(';')
84 for wrkld
in workloads
:
85 process
= LiveProcess()
86 process
.executable
= wrkld
89 process
.cmd
= [wrkld
] + pargs
[idx
].split()
94 process
.input = inputs
[idx
]
95 if len(outputs
) > idx
:
96 process
.output
= outputs
[idx
]
97 if len(errouts
) > idx
:
98 process
.errout
= errouts
[idx
]
100 multiprocesses
.append(process
)
104 assert(options
.cpu_type
== "detailed" or options
.cpu_type
== "inorder")
105 return multiprocesses
, idx
107 return multiprocesses
, 1
110 parser
= optparse
.OptionParser()
111 Options
.addCommonOptions(parser
)
112 Options
.addSEOptions(parser
)
114 if '--ruby' in sys
.argv
:
115 Ruby
.define_options(parser
)
117 (options
, args
) = parser
.parse_args()
120 print "Error: script doesn't take any positional arguments"
127 apps
= options
.bench
.split("-")
128 if len(apps
) != options
.num_cpus
:
129 print "number of benchmarks not equal to set num_cpus!"
134 if buildEnv
['TARGET_ISA'] == 'alpha':
135 exec("workload = %s('alpha', 'tru64', 'ref')" % app
)
137 exec("workload = %s(buildEnv['TARGET_ISA'], 'linux', 'ref')" % app
)
138 multiprocesses
.append(workload
.makeLiveProcess())
140 print >>sys
.stderr
, "Unable to find workload for %s: %s" % (buildEnv
['TARGET_ISA'], app
)
143 multiprocesses
, numThreads
= get_processes(options
)
145 print >> sys
.stderr
, "No workload specified. Exiting!\n"
149 (CPUClass
, test_mem_mode
, FutureClass
) = Simulation
.setCPUClass(options
)
150 CPUClass
.clock
= options
.clock
151 CPUClass
.numThreads
= numThreads
153 # Check -- do not allow SMT with multiple CPUs
154 if options
.smt
and options
.num_cpus
> 1:
155 fatal("You cannot use SMT with multiple CPUs!")
157 np
= options
.num_cpus
158 system
= System(cpu
= [CPUClass(cpu_id
=i
) for i
in xrange(np
)],
159 physmem
= SimpleMemory(range=AddrRange("512MB")),
160 membus
= CoherentBus(), mem_mode
= test_mem_mode
)
164 if CPUClass
!= AtomicSimpleCPU
:
165 fatal("Fastmem can only be used with atomic CPU!")
166 if (options
.caches
or options
.l2cache
):
167 fatal("You cannot use fastmem in combination with caches!")
171 system
.cpu
[i
].workload
= multiprocesses
172 elif len(multiprocesses
) == 1:
173 system
.cpu
[i
].workload
= multiprocesses
[0]
175 system
.cpu
[i
].workload
= multiprocesses
[i
]
178 system
.cpu
[i
].fastmem
= True
181 system
.cpu
[i
].addCheckerCpu()
183 system
.cpu
[i
].createThreads()
186 if not (options
.cpu_type
== "detailed" or options
.cpu_type
== "timing"):
187 print >> sys
.stderr
, "Ruby requires TimingSimpleCPU or O3CPU!!"
190 # Set the option for physmem so that it is not allocated any space
191 system
.physmem
.null
= True
193 options
.use_map
= True
194 Ruby
.create_system(options
, system
)
195 assert(options
.num_cpus
== len(system
.ruby
._cpu
_ruby
_ports
))
198 ruby_port
= system
.ruby
._cpu
_ruby
_ports
[i
]
200 # Create the interrupt controller and connect its ports to Ruby
201 # Note that the interrupt controller is always present but only
202 # in x86 does it have message ports that need to be connected
203 system
.cpu
[i
].createInterruptController()
205 # Connect the cpu's cache ports to Ruby
206 system
.cpu
[i
].icache_port
= ruby_port
.slave
207 system
.cpu
[i
].dcache_port
= ruby_port
.slave
208 if buildEnv
['TARGET_ISA'] == 'x86':
209 system
.cpu
[i
].interrupts
.pio
= ruby_port
.master
210 system
.cpu
[i
].interrupts
.int_master
= ruby_port
.slave
211 system
.cpu
[i
].interrupts
.int_slave
= ruby_port
.master
212 system
.cpu
[i
].itb
.walker
.port
= ruby_port
.slave
213 system
.cpu
[i
].dtb
.walker
.port
= ruby_port
.slave
215 system
.system_port
= system
.membus
.slave
216 system
.physmem
.port
= system
.membus
.master
217 CacheConfig
.config_cache(options
, system
)
219 root
= Root(full_system
= False, system
= system
)
220 Simulation
.run(options
, root
, system
, FutureClass
)