1 # -*- coding: utf-8 -*-
2 # Copyright (c) 2015 Jason Power
5 # Redistribution and use in source and binary forms, with or without
6 # modification, are permitted provided that the following conditions are
7 # met: redistributions of source code must retain the above copyright
8 # notice, this list of conditions and the following disclaimer;
9 # redistributions in binary form must reproduce the above copyright
10 # notice, this list of conditions and the following disclaimer in the
11 # documentation and/or other materials provided with the distribution;
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13 # contributors may be used to endorse or promote products derived from
14 # this software without specific prior written permission.
16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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28 """ Caches with options for a simple gem5 configuration script
30 This file contains L1 I/D and L2 caches to be used in the simple
31 gem5 configuration script. It uses the SimpleOpts wrapper to set up command
32 line options from each individual class.
35 from __future__
import print_function
36 from __future__
import absolute_import
39 from m5
.objects
import Cache
41 # Add the common scripts to our path
42 m5
.util
.addToPath('../../')
44 from common
import SimpleOpts
46 # Some specific options for caches
47 # For all options see src/mem/cache/BaseCache.py
50 """Simple L1 Cache with default values"""
59 def __init__(self
, options
=None):
60 super(L1Cache
, self
).__init
__()
63 def connectBus(self
, bus
):
64 """Connect this cache to a memory-side bus"""
65 self
.mem_side
= bus
.slave
67 def connectCPU(self
, cpu
):
68 """Connect this cache's port to a CPU-side port
69 This must be defined in a subclass"""
70 raise NotImplementedError
72 class L1ICache(L1Cache
):
73 """Simple L1 instruction cache with default values"""
75 # Set the default size
78 SimpleOpts
.add_option('--l1i_size',
79 help="L1 instruction cache size. Default: %s" % size
)
81 def __init__(self
, opts
=None):
82 super(L1ICache
, self
).__init
__(opts
)
83 if not opts
or not opts
.l1i_size
:
85 self
.size
= opts
.l1i_size
87 def connectCPU(self
, cpu
):
88 """Connect this cache's port to a CPU icache port"""
89 self
.cpu_side
= cpu
.icache_port
91 class L1DCache(L1Cache
):
92 """Simple L1 data cache with default values"""
94 # Set the default size
97 SimpleOpts
.add_option('--l1d_size',
98 help="L1 data cache size. Default: %s" % size
)
100 def __init__(self
, opts
=None):
101 super(L1DCache
, self
).__init
__(opts
)
102 if not opts
or not opts
.l1d_size
:
104 self
.size
= opts
.l1d_size
106 def connectCPU(self
, cpu
):
107 """Connect this cache's port to a CPU dcache port"""
108 self
.cpu_side
= cpu
.dcache_port
110 class L2Cache(Cache
):
111 """Simple L2 Cache with default values"""
118 response_latency
= 20
122 SimpleOpts
.add_option('--l2_size', help="L2 cache size. Default: %s" % size
)
124 def __init__(self
, opts
=None):
125 super(L2Cache
, self
).__init
__()
126 if not opts
or not opts
.l2_size
:
128 self
.size
= opts
.l2_size
130 def connectCPUSideBus(self
, bus
):
131 self
.cpu_side
= bus
.master
133 def connectMemSideBus(self
, bus
):
134 self
.mem_side
= bus
.slave