configs/learning_gem5/part1/caches.py

   1 # -*- coding: utf-8 -*-
   2 # Copyright (c) 2015 Jason Power
   3 # All rights reserved.
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   5 # Redistribution and use in source and binary forms, with or without
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  27
  28 """ Caches with options for a simple gem5 configuration script
  29
  30 This file contains L1 I/D and L2 caches to be used in the simple
  31 gem5 configuration script. It uses the SimpleOpts wrapper to set up command
  32 line options from each individual class.
  33 """
  34
  35 from __future__ import print_function
  36 from __future__ import absolute_import
  37
  38 import m5
  39 from m5.objects import Cache
  40
  41 # Add the common scripts to our path
  42 m5.util.addToPath('../../')
  43
  44 from common import SimpleOpts
  45
  46 # Some specific options for caches
  47 # For all options see src/mem/cache/BaseCache.py
  48
  49 class L1Cache(Cache):
  50     """Simple L1 Cache with default values"""
  51
  52     assoc = 2
  53     tag_latency = 2
  54     data_latency = 2
  55     response_latency = 2
  56     mshrs = 4
  57     tgts_per_mshr = 20
  58
  59     def __init__(self, options=None):
  60         super(L1Cache, self).__init__()
  61         pass
  62
  63     def connectBus(self, bus):
  64         """Connect this cache to a memory-side bus"""
  65         self.mem_side = bus.slave
  66
  67     def connectCPU(self, cpu):
  68         """Connect this cache's port to a CPU-side port
  69            This must be defined in a subclass"""
  70         raise NotImplementedError
  71
  72 class L1ICache(L1Cache):
  73     """Simple L1 instruction cache with default values"""
  74
  75     # Set the default size
  76     size = '16kB'
  77
  78     SimpleOpts.add_option('--l1i_size',
  79                           help="L1 instruction cache size. Default: %s" % size)
  80
  81     def __init__(self, opts=None):
  82         super(L1ICache, self).__init__(opts)
  83         if not opts or not opts.l1i_size:
  84             return
  85         self.size = opts.l1i_size
  86
  87     def connectCPU(self, cpu):
  88         """Connect this cache's port to a CPU icache port"""
  89         self.cpu_side = cpu.icache_port
  90
  91 class L1DCache(L1Cache):
  92     """Simple L1 data cache with default values"""
  93
  94     # Set the default size
  95     size = '64kB'
  96
  97     SimpleOpts.add_option('--l1d_size',
  98                           help="L1 data cache size. Default: %s" % size)
  99
 100     def __init__(self, opts=None):
 101         super(L1DCache, self).__init__(opts)
 102         if not opts or not opts.l1d_size:
 103             return
 104         self.size = opts.l1d_size
 105
 106     def connectCPU(self, cpu):
 107         """Connect this cache's port to a CPU dcache port"""
 108         self.cpu_side = cpu.dcache_port
 109
 110 class L2Cache(Cache):
 111     """Simple L2 Cache with default values"""
 112
 113     # Default parameters
 114     size = '256kB'
 115     assoc = 8
 116     tag_latency = 20
 117     data_latency = 20
 118     response_latency = 20
 119     mshrs = 20
 120     tgts_per_mshr = 12
 121
 122     SimpleOpts.add_option('--l2_size', help="L2 cache size. Default: %s" % size)
 123
 124     def __init__(self, opts=None):
 125         super(L2Cache, self).__init__()
 126         if not opts or not opts.l2_size:
 127             return
 128         self.size = opts.l2_size
 129
 130     def connectCPUSideBus(self, bus):
 131         self.cpu_side = bus.master
 132
 133     def connectMemSideBus(self, bus):
 134         self.mem_side = bus.slave