configs/learning_gem5/part1/caches.py

   1 # -*- coding: utf-8 -*-
   2 # Copyright (c) 2015 Jason Power
   3 # All rights reserved.
   4 #
   5 # Redistribution and use in source and binary forms, with or without
   6 # modification, are permitted provided that the following conditions are
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  10 # notice, this list of conditions and the following disclaimer in the
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  14 # this software without specific prior written permission.
  15 #
  16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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  27 #
  28 # Authors: Jason Power
  29
  30 """ Caches with options for a simple gem5 configuration script
  31
  32 This file contains L1 I/D and L2 caches to be used in the simple
  33 gem5 configuration script. It uses the SimpleOpts wrapper to set up command
  34 line options from each individual class.
  35 """
  36
  37 from m5.objects import Cache
  38
  39 from common import SimpleOpts
  40
  41 # Some specific options for caches
  42 # For all options see src/mem/cache/BaseCache.py
  43
  44 class L1Cache(Cache):
  45     """Simple L1 Cache with default values"""
  46
  47     assoc = 2
  48     tag_latency = 2
  49     data_latency = 2
  50     response_latency = 2
  51     mshrs = 4
  52     tgts_per_mshr = 20
  53
  54     def __init__(self, options=None):
  55         super(L1Cache, self).__init__()
  56         pass
  57
  58     def connectBus(self, bus):
  59         """Connect this cache to a memory-side bus"""
  60         self.mem_side = bus.slave
  61
  62     def connectCPU(self, cpu):
  63         """Connect this cache's port to a CPU-side port
  64            This must be defined in a subclass"""
  65         raise NotImplementedError
  66
  67 class L1ICache(L1Cache):
  68     """Simple L1 instruction cache with default values"""
  69
  70     # Set the default size
  71     size = '16kB'
  72
  73     SimpleOpts.add_option('--l1i_size',
  74                           help="L1 instruction cache size. Default: %s" % size)
  75
  76     def __init__(self, opts=None):
  77         super(L1ICache, self).__init__(opts)
  78         if not opts or not opts.l1i_size:
  79             return
  80         self.size = opts.l1i_size
  81
  82     def connectCPU(self, cpu):
  83         """Connect this cache's port to a CPU icache port"""
  84         self.cpu_side = cpu.icache_port
  85
  86 class L1DCache(L1Cache):
  87     """Simple L1 data cache with default values"""
  88
  89     # Set the default size
  90     size = '64kB'
  91
  92     SimpleOpts.add_option('--l1d_size',
  93                           help="L1 data cache size. Default: %s" % size)
  94
  95     def __init__(self, opts=None):
  96         super(L1DCache, self).__init__(opts)
  97         if not opts or not opts.l1d_size:
  98             return
  99         self.size = opts.l1d_size
 100
 101     def connectCPU(self, cpu):
 102         """Connect this cache's port to a CPU dcache port"""
 103         self.cpu_side = cpu.dcache_port
 104
 105 class L2Cache(Cache):
 106     """Simple L2 Cache with default values"""
 107
 108     # Default parameters
 109     size = '256kB'
 110     assoc = 8
 111     tag_latency = 20
 112     data_latency = 20
 113     response_latency = 20
 114     mshrs = 20
 115     tgts_per_mshr = 12
 116
 117     SimpleOpts.add_option('--l2_size', help="L2 cache size. Default: %s" % size)
 118
 119     def __init__(self, opts=None):
 120         super(L2Cache, self).__init__()
 121         if not opts or not opts.l2_size:
 122             return
 123         self.size = opts.l2_size
 124
 125     def connectCPUSideBus(self, bus):
 126         self.cpu_side = bus.master
 127
 128     def connectMemSideBus(self, bus):
 129         self.mem_side = bus.slave