configs/learning_gem5/part1/two_level.py

   1 # -*- coding: utf-8 -*-
   2 # Copyright (c) 2015 Jason Power
   3 # All rights reserved.
   4 #
   5 # Redistribution and use in source and binary forms, with or without
   6 # modification, are permitted provided that the following conditions are
   7 # met: redistributions of source code must retain the above copyright
   8 # notice, this list of conditions and the following disclaimer;
   9 # redistributions in binary form must reproduce the above copyright
  10 # notice, this list of conditions and the following disclaimer in the
  11 # documentation and/or other materials provided with the distribution;
  12 # neither the name of the copyright holders nor the names of its
  13 # contributors may be used to endorse or promote products derived from
  14 # this software without specific prior written permission.
  15 #
  16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27
  28 """ This file creates a single CPU and a two-level cache system.
  29 This script takes a single parameter which specifies a binary to execute.
  30 If none is provided it executes 'hello' by default (mostly used for testing)
  31
  32 See Part 1, Chapter 3: Adding cache to the configuration script in the
  33 learning_gem5 book for more information about this script.
  34 This file exports options for the L1 I/D and L2 cache sizes.
  35
  36 IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
  37            also needs to be updated. For now, email Jason <power.jg@gmail.com>
  38
  39 """
  40
  41 from __future__ import print_function
  42 from __future__ import absolute_import
  43
  44 # import the m5 (gem5) library created when gem5 is built
  45 import m5
  46 # import all of the SimObjects
  47 from m5.objects import *
  48
  49 # Add the common scripts to our path
  50 m5.util.addToPath('../../')
  51
  52 # import the caches which we made
  53 from caches import *
  54
  55 # import the SimpleOpts module
  56 from common import SimpleOpts
  57
  58 # Set the usage message to display
  59 SimpleOpts.set_usage("usage: %prog [options] <binary to execute>")
  60
  61 # Finalize the arguments and grab the opts so we can pass it on to our objects
  62 (opts, args) = SimpleOpts.parse_args()
  63
  64 # get ISA for the default binary to run. This is mostly for simple testing
  65 isa = str(m5.defines.buildEnv['TARGET_ISA']).lower()
  66
  67 # Default to running 'hello', use the compiled ISA to find the binary
  68 # grab the specific path to the binary
  69 thispath = os.path.dirname(os.path.realpath(__file__))
  70 binary = os.path.join(thispath, '../../../',
  71                       'tests/test-progs/hello/bin/', isa, 'linux/hello')
  72
  73 # Check if there was a binary passed in via the command line and error if
  74 # there are too many arguments
  75 if len(args) == 1:
  76     binary = args[0]
  77 elif len(args) > 1:
  78     SimpleOpts.print_help()
  79     m5.fatal("Expected a binary to execute as positional argument")
  80
  81 # create the system we are going to simulate
  82 system = System()
  83
  84 # Set the clock fequency of the system (and all of its children)
  85 system.clk_domain = SrcClockDomain()
  86 system.clk_domain.clock = '1GHz'
  87 system.clk_domain.voltage_domain = VoltageDomain()
  88
  89 # Set up the system
  90 system.mem_mode = 'timing'               # Use timing accesses
  91 system.mem_ranges = [AddrRange('512MB')] # Create an address range
  92
  93 # Create a simple CPU
  94 system.cpu = TimingSimpleCPU()
  95
  96 # Create an L1 instruction and data cache
  97 system.cpu.icache = L1ICache(opts)
  98 system.cpu.dcache = L1DCache(opts)
  99
 100 # Connect the instruction and data caches to the CPU
 101 system.cpu.icache.connectCPU(system.cpu)
 102 system.cpu.dcache.connectCPU(system.cpu)
 103
 104 # Create a memory bus, a coherent crossbar, in this case
 105 system.l2bus = L2XBar()
 106
 107 # Hook the CPU ports up to the l2bus
 108 system.cpu.icache.connectBus(system.l2bus)
 109 system.cpu.dcache.connectBus(system.l2bus)
 110
 111 # Create an L2 cache and connect it to the l2bus
 112 system.l2cache = L2Cache(opts)
 113 system.l2cache.connectCPUSideBus(system.l2bus)
 114
 115 # Create a memory bus
 116 system.membus = SystemXBar()
 117
 118 # Connect the L2 cache to the membus
 119 system.l2cache.connectMemSideBus(system.membus)
 120
 121 # create the interrupt controller for the CPU
 122 system.cpu.createInterruptController()
 123
 124 # For x86 only, make sure the interrupts are connected to the memory
 125 # Note: these are directly connected to the memory bus and are not cached
 126 if m5.defines.buildEnv['TARGET_ISA'] == "x86":
 127     system.cpu.interrupts[0].pio = system.membus.master
 128     system.cpu.interrupts[0].int_master = system.membus.slave
 129     system.cpu.interrupts[0].int_slave = system.membus.master
 130
 131 # Connect the system up to the membus
 132 system.system_port = system.membus.slave
 133
 134 # Create a DDR3 memory controller
 135 system.mem_ctrl = DDR3_1600_8x8()
 136 system.mem_ctrl.range = system.mem_ranges[0]
 137 system.mem_ctrl.port = system.membus.master
 138
 139 # Create a process for a simple "Hello World" application
 140 process = Process()
 141 # Set the command
 142 # cmd is a list which begins with the executable (like argv)
 143 process.cmd = [binary]
 144 # Set the cpu to use the process as its workload and create thread contexts
 145 system.cpu.workload = process
 146 system.cpu.createThreads()
 147
 148 # set up the root SimObject and start the simulation
 149 root = Root(full_system = False, system = system)
 150 # instantiate all of the objects we've created above
 151 m5.instantiate()
 152
 153 print("Beginning simulation!")
 154 exit_event = m5.simulate()
 155 print('Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()))