configs/learning_gem5/part1/two_level.py

   1 # -*- coding: utf-8 -*-
   2 # Copyright (c) 2015 Jason Power
   3 # All rights reserved.
   4 #
   5 # Redistribution and use in source and binary forms, with or without
   6 # modification, are permitted provided that the following conditions are
   7 # met: redistributions of source code must retain the above copyright
   8 # notice, this list of conditions and the following disclaimer;
   9 # redistributions in binary form must reproduce the above copyright
  10 # notice, this list of conditions and the following disclaimer in the
  11 # documentation and/or other materials provided with the distribution;
  12 # neither the name of the copyright holders nor the names of its
  13 # contributors may be used to endorse or promote products derived from
  14 # this software without specific prior written permission.
  15 #
  16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27 #
  28 # Authors: Jason Power
  29
  30 """ This file creates a single CPU and a two-level cache system.
  31 This script takes a single parameter which specifies a binary to execute.
  32 If none is provided it executes 'hello' by default (mostly used for testing)
  33
  34 See Part 1, Chapter 3: Adding cache to the configuration script in the
  35 learning_gem5 book for more information about this script.
  36 This file exports options for the L1 I/D and L2 cache sizes.
  37
  38 IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
  39            also needs to be updated. For now, email Jason <power.jg@gmail.com>
  40
  41 """
  42
  43 # import the m5 (gem5) library created when gem5 is built
  44 import m5
  45 # import all of the SimObjects
  46 from m5.objects import *
  47
  48 # Add the common scripts to our path
  49 m5.util.addToPath('../../')
  50
  51 # import the caches which we made
  52 from caches import *
  53
  54 # import the SimpleOpts module
  55 from common import SimpleOpts
  56
  57 # Set the usage message to display
  58 SimpleOpts.set_usage("usage: %prog [options] <binary to execute>")
  59
  60 # Finalize the arguments and grab the opts so we can pass it on to our objects
  61 (opts, args) = SimpleOpts.parse_args()
  62
  63 # get ISA for the default binary to run. This is mostly for simple testing
  64 isa = str(m5.defines.buildEnv['TARGET_ISA']).lower()
  65
  66 # Default to running 'hello', use the compiled ISA to find the binary
  67 binary = 'tests/test-progs/hello/bin/' + isa + '/linux/hello'
  68
  69 # Check if there was a binary passed in via the command line and error if
  70 # there are too many arguments
  71 if len(args) == 1:
  72     binary = args[0]
  73 elif len(args) > 1:
  74     SimpleOpts.print_help()
  75     m5.fatal("Expected a binary to execute as positional argument")
  76
  77 # create the system we are going to simulate
  78 system = System()
  79
  80 # Set the clock fequency of the system (and all of its children)
  81 system.clk_domain = SrcClockDomain()
  82 system.clk_domain.clock = '1GHz'
  83 system.clk_domain.voltage_domain = VoltageDomain()
  84
  85 # Set up the system
  86 system.mem_mode = 'timing'               # Use timing accesses
  87 system.mem_ranges = [AddrRange('512MB')] # Create an address range
  88
  89 # Create a simple CPU
  90 system.cpu = TimingSimpleCPU()
  91
  92 # Create an L1 instruction and data cache
  93 system.cpu.icache = L1ICache(opts)
  94 system.cpu.dcache = L1DCache(opts)
  95
  96 # Connect the instruction and data caches to the CPU
  97 system.cpu.icache.connectCPU(system.cpu)
  98 system.cpu.dcache.connectCPU(system.cpu)
  99
 100 # Create a memory bus, a coherent crossbar, in this case
 101 system.l2bus = L2XBar()
 102
 103 # Hook the CPU ports up to the l2bus
 104 system.cpu.icache.connectBus(system.l2bus)
 105 system.cpu.dcache.connectBus(system.l2bus)
 106
 107 # Create an L2 cache and connect it to the l2bus
 108 system.l2cache = L2Cache(opts)
 109 system.l2cache.connectCPUSideBus(system.l2bus)
 110
 111 # Create a memory bus
 112 system.membus = SystemXBar()
 113
 114 # Connect the L2 cache to the membus
 115 system.l2cache.connectMemSideBus(system.membus)
 116
 117 # create the interrupt controller for the CPU
 118 system.cpu.createInterruptController()
 119
 120 # For x86 only, make sure the interrupts are connected to the memory
 121 # Note: these are directly connected to the memory bus and are not cached
 122 if m5.defines.buildEnv['TARGET_ISA'] == "x86":
 123     system.cpu.interrupts[0].pio = system.membus.master
 124     system.cpu.interrupts[0].int_master = system.membus.slave
 125     system.cpu.interrupts[0].int_slave = system.membus.master
 126
 127 # Connect the system up to the membus
 128 system.system_port = system.membus.slave
 129
 130 # Create a DDR3 memory controller
 131 system.mem_ctrl = DDR3_1600_x64()
 132 system.mem_ctrl.range = system.mem_ranges[0]
 133 system.mem_ctrl.port = system.membus.master
 134
 135 # Create a process for a simple "Hello World" application
 136 process = LiveProcess()
 137 # Set the command
 138 # cmd is a list which begins with the executable (like argv)
 139 process.cmd = [binary]
 140 # Set the cpu to use the process as its workload and create thread contexts
 141 system.cpu.workload = process
 142 system.cpu.createThreads()
 143
 144 # set up the root SimObject and start the simulation
 145 root = Root(full_system = False, system = system)
 146 # instantiate all of the objects we've created above
 147 m5.instantiate()
 148
 149 print "Beginning simulation!"
 150 exit_event = m5.simulate()
 151 print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause())