1 # -*- coding: utf-8 -*-
2 # Copyright (c) 2017 Jason Lowe-Power
5 # Redistribution and use in source and binary forms, with or without
6 # modification, are permitted provided that the following conditions are
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28 """ This file creates a barebones system and executes 'hello', a simple Hello
29 World application. Adds a simple cache between the CPU and the membus.
31 This config file assumes that the x86 ISA was built.
34 from __future__
import print_function
35 from __future__
import absolute_import
37 # import the m5 (gem5) library created when gem5 is built
39 # import all of the SimObjects
40 from m5
.objects
import *
42 # create the system we are going to simulate
45 # Set the clock fequency of the system (and all of its children)
46 system
.clk_domain
= SrcClockDomain()
47 system
.clk_domain
.clock
= '1GHz'
48 system
.clk_domain
.voltage_domain
= VoltageDomain()
51 system
.mem_mode
= 'timing' # Use timing accesses
52 system
.mem_ranges
= [AddrRange('512MB')] # Create an address range
55 system
.cpu
= TimingSimpleCPU()
57 # Create a memory bus, a coherent crossbar, in this case
58 system
.membus
= SystemXBar()
60 # Create a simple cache
61 system
.cache
= SimpleCache(size
='1kB')
63 # Connect the I and D cache ports of the CPU to the memobj.
64 # Since cpu_side is a vector port, each time one of these is connected, it will
65 # create a new instance of the CPUSidePort class
66 system
.cpu
.icache_port
= system
.cache
.cpu_side
67 system
.cpu
.dcache_port
= system
.cache
.cpu_side
69 # Hook the cache up to the memory bus
70 system
.cache
.mem_side
= system
.membus
.slave
72 # create the interrupt controller for the CPU and connect to the membus
73 system
.cpu
.createInterruptController()
74 system
.cpu
.interrupts
[0].pio
= system
.membus
.master
75 system
.cpu
.interrupts
[0].int_master
= system
.membus
.slave
76 system
.cpu
.interrupts
[0].int_slave
= system
.membus
.master
78 # Create a DDR3 memory controller and connect it to the membus
79 system
.mem_ctrl
= DDR3_1600_8x8()
80 system
.mem_ctrl
.range = system
.mem_ranges
[0]
81 system
.mem_ctrl
.port
= system
.membus
.master
83 # Connect the system up to the membus
84 system
.system_port
= system
.membus
.slave
86 # Create a process for a simple "Hello World" application
89 # grab the specific path to the binary
90 thispath
= os
.path
.dirname(os
.path
.realpath(__file__
))
91 binpath
= os
.path
.join(thispath
, '../../../',
92 'tests/test-progs/hello/bin/x86/linux/hello')
93 # cmd is a list which begins with the executable (like argv)
94 process
.cmd
= [binpath
]
95 # Set the cpu to use the process as its workload and create thread contexts
96 system
.cpu
.workload
= process
97 system
.cpu
.createThreads()
99 # set up the root SimObject and start the simulation
100 root
= Root(full_system
= False, system
= system
)
101 # instantiate all of the objects we've created above
104 print("Beginning simulation!")
105 exit_event
= m5
.simulate()
106 print('Exiting @ tick %i because %s' % (m5
.curTick(), exit_event
.getCause()))