configs/learning_gem5/part2/simple_cache.py

   1 # -*- coding: utf-8 -*-
   2 # Copyright (c) 2017 Jason Lowe-Power
   3 # All rights reserved.
   4 #
   5 # Redistribution and use in source and binary forms, with or without
   6 # modification, are permitted provided that the following conditions are
   7 # met: redistributions of source code must retain the above copyright
   8 # notice, this list of conditions and the following disclaimer;
   9 # redistributions in binary form must reproduce the above copyright
  10 # notice, this list of conditions and the following disclaimer in the
  11 # documentation and/or other materials provided with the distribution;
  12 # neither the name of the copyright holders nor the names of its
  13 # contributors may be used to endorse or promote products derived from
  14 # this software without specific prior written permission.
  15 #
  16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27
  28 """ This file creates a barebones system and executes 'hello', a simple Hello
  29 World application. Adds a simple cache between the CPU and the membus.
  30
  31 This config file assumes that the x86 ISA was built.
  32 """
  33
  34 from __future__ import print_function
  35 from __future__ import absolute_import
  36
  37 # import the m5 (gem5) library created when gem5 is built
  38 import m5
  39 # import all of the SimObjects
  40 from m5.objects import *
  41
  42 # create the system we are going to simulate
  43 system = System()
  44
  45 # Set the clock fequency of the system (and all of its children)
  46 system.clk_domain = SrcClockDomain()
  47 system.clk_domain.clock = '1GHz'
  48 system.clk_domain.voltage_domain = VoltageDomain()
  49
  50 # Set up the system
  51 system.mem_mode = 'timing'               # Use timing accesses
  52 system.mem_ranges = [AddrRange('512MB')] # Create an address range
  53
  54 # Create a simple CPU
  55 system.cpu = TimingSimpleCPU()
  56
  57 # Create a memory bus, a coherent crossbar, in this case
  58 system.membus = SystemXBar()
  59
  60 # Create a simple cache
  61 system.cache = SimpleCache(size='1kB')
  62
  63 # Connect the I and D cache ports of the CPU to the memobj.
  64 # Since cpu_side is a vector port, each time one of these is connected, it will
  65 # create a new instance of the CPUSidePort class
  66 system.cpu.icache_port = system.cache.cpu_side
  67 system.cpu.dcache_port = system.cache.cpu_side
  68
  69 # Hook the cache up to the memory bus
  70 system.cache.mem_side = system.membus.slave
  71
  72 # create the interrupt controller for the CPU and connect to the membus
  73 system.cpu.createInterruptController()
  74 system.cpu.interrupts[0].pio = system.membus.master
  75 system.cpu.interrupts[0].int_master = system.membus.slave
  76 system.cpu.interrupts[0].int_slave = system.membus.master
  77
  78 # Create a DDR3 memory controller and connect it to the membus
  79 system.mem_ctrl = DRAMCtrl()
  80 system.mem_ctrl.dram = DDR3_1600_8x8()
  81 system.mem_ctrl.dram.range = system.mem_ranges[0]
  82 system.mem_ctrl.port = system.membus.master
  83
  84 # Connect the system up to the membus
  85 system.system_port = system.membus.slave
  86
  87 # Create a process for a simple "Hello World" application
  88 process = Process()
  89 # Set the command
  90 # grab the specific path to the binary
  91 thispath = os.path.dirname(os.path.realpath(__file__))
  92 binpath = os.path.join(thispath, '../../../',
  93                        'tests/test-progs/hello/bin/x86/linux/hello')
  94 # cmd is a list which begins with the executable (like argv)
  95 process.cmd = [binpath]
  96 # Set the cpu to use the process as its workload and create thread contexts
  97 system.cpu.workload = process
  98 system.cpu.createThreads()
  99
 100 # set up the root SimObject and start the simulation
 101 root = Root(full_system = False, system = system)
 102 # instantiate all of the objects we've created above
 103 m5.instantiate()
 104
 105 print("Beginning simulation!")
 106 exit_event = m5.simulate()
 107 print('Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()))