configs/learning_gem5/part2/simple_memobj.py

   1 # -*- coding: utf-8 -*-
   2 # Copyright (c) 2017 Jason Lowe-Power
   3 # All rights reserved.
   4 #
   5 # Redistribution and use in source and binary forms, with or without
   6 # modification, are permitted provided that the following conditions are
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  15 #
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  27
  28 """ This file creates a barebones system and executes 'hello', a simple Hello
  29 World application. Adds a simple memobj between the CPU and the membus.
  30
  31 This config file assumes that the x86 ISA was built.
  32 """
  33
  34 from __future__ import print_function
  35 from __future__ import absolute_import
  36
  37 # import the m5 (gem5) library created when gem5 is built
  38 import m5
  39 # import all of the SimObjects
  40 from m5.objects import *
  41
  42 # create the system we are going to simulate
  43 system = System()
  44
  45 # Set the clock fequency of the system (and all of its children)
  46 system.clk_domain = SrcClockDomain()
  47 system.clk_domain.clock = '1GHz'
  48 system.clk_domain.voltage_domain = VoltageDomain()
  49
  50 # Set up the system
  51 system.mem_mode = 'timing'               # Use timing accesses
  52 system.mem_ranges = [AddrRange('512MB')] # Create an address range
  53
  54 # Create a simple CPU
  55 system.cpu = TimingSimpleCPU()
  56
  57 # Create the simple memory object
  58 system.memobj = SimpleMemobj()
  59
  60 # Hook the CPU ports up to the cache
  61 system.cpu.icache_port = system.memobj.inst_port
  62 system.cpu.dcache_port = system.memobj.data_port
  63
  64 # Create a memory bus, a coherent crossbar, in this case
  65 system.membus = SystemXBar()
  66
  67 # Connect the memobj
  68 system.memobj.mem_side = system.membus.slave
  69
  70 # create the interrupt controller for the CPU and connect to the membus
  71 system.cpu.createInterruptController()
  72 system.cpu.interrupts[0].pio = system.membus.master
  73 system.cpu.interrupts[0].int_master = system.membus.slave
  74 system.cpu.interrupts[0].int_slave = system.membus.master
  75
  76 # Create a DDR3 memory controller and connect it to the membus
  77 system.mem_ctrl = DDR3_1600_8x8()
  78 system.mem_ctrl.range = system.mem_ranges[0]
  79 system.mem_ctrl.port = system.membus.master
  80
  81 # Connect the system up to the membus
  82 system.system_port = system.membus.slave
  83
  84 # Create a process for a simple "Hello World" application
  85 process = Process()
  86 # Set the command
  87 # grab the specific path to the binary
  88 thispath = os.path.dirname(os.path.realpath(__file__))
  89 binpath = os.path.join(thispath, '../../../',
  90                        'tests/test-progs/hello/bin/x86/linux/hello')
  91 # cmd is a list which begins with the executable (like argv)
  92 process.cmd = [binpath]
  93 # Set the cpu to use the process as its workload and create thread contexts
  94 system.cpu.workload = process
  95 system.cpu.createThreads()
  96
  97 # set up the root SimObject and start the simulation
  98 root = Root(full_system = False, system = system)
  99 # instantiate all of the objects we've created above
 100 m5.instantiate()
 101
 102 print("Beginning simulation!")
 103 exit_event = m5.simulate()
 104 print('Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()))