configs/learning_gem5/part3/msi_caches.py

   1 # -*- coding: utf-8 -*-
   2 # Copyright (c) 2017 Jason Power
   3 # All rights reserved.
   4 #
   5 # Redistribution and use in source and binary forms, with or without
   6 # modification, are permitted provided that the following conditions are
   7 # met: redistributions of source code must retain the above copyright
   8 # notice, this list of conditions and the following disclaimer;
   9 # redistributions in binary form must reproduce the above copyright
  10 # notice, this list of conditions and the following disclaimer in the
  11 # documentation and/or other materials provided with the distribution;
  12 # neither the name of the copyright holders nor the names of its
  13 # contributors may be used to endorse or promote products derived from
  14 # this software without specific prior written permission.
  15 #
  16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27
  28 """ This file creates a set of Ruby caches, the Ruby network, and a simple
  29 point-to-point topology.
  30 See Part 3 in the Learning gem5 book:
  31 http://gem5.org/documentation/learning_gem5/part3/MSIintro
  32
  33 IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
  34            also needs to be updated. For now, email Jason <jason@lowepower.com>
  35
  36 """
  37
  38 import math
  39
  40 from m5.defines import buildEnv
  41 from m5.util import fatal, panic
  42
  43 from m5.objects import *
  44
  45 class MyCacheSystem(RubySystem):
  46
  47     def __init__(self):
  48         if buildEnv['PROTOCOL'] != 'MSI':
  49             fatal("This system assumes MSI from learning gem5!")
  50
  51         super(MyCacheSystem, self).__init__()
  52
  53     def setup(self, system, cpus, mem_ctrls):
  54         """Set up the Ruby cache subsystem. Note: This can't be done in the
  55            constructor because many of these items require a pointer to the
  56            ruby system (self). This causes infinite recursion in initialize()
  57            if we do this in the __init__.
  58         """
  59         # Ruby's global network.
  60         self.network = MyNetwork(self)
  61
  62         # MSI uses 3 virtual networks. One for requests (lowest priority), one
  63         # for responses (highest priority), and one for "forwards" or
  64         # cache-to-cache requests. See *.sm files for details.
  65         self.number_of_virtual_networks = 3
  66         self.network.number_of_virtual_networks = 3
  67
  68         # There is a single global list of all of the controllers to make it
  69         # easier to connect everything to the global network. This can be
  70         # customized depending on the topology/network requirements.
  71         # Create one controller for each L1 cache (and the cache mem obj.)
  72         # Create a single directory controller (Really the memory cntrl)
  73         self.controllers = \
  74             [L1Cache(system, self, cpu) for cpu in cpus] + \
  75             [DirController(self, system.mem_ranges, mem_ctrls)]
  76
  77         # Create one sequencer per CPU. In many systems this is more
  78         # complicated since you have to create sequencers for DMA controllers
  79         # and other controllers, too.
  80         self.sequencers = [RubySequencer(version = i,
  81                                 # I/D cache is combined and grab from ctrl
  82                                 dcache = self.controllers[i].cacheMemory,
  83                                 clk_domain = self.controllers[i].clk_domain,
  84                                 ) for i in range(len(cpus))]
  85
  86         # We know that we put the controllers in an order such that the first
  87         # N of them are the L1 caches which need a sequencer pointer
  88         for i,c in enumerate(self.controllers[0:len(self.sequencers)]):
  89             c.sequencer = self.sequencers[i]
  90
  91         self.num_of_sequencers = len(self.sequencers)
  92
  93         # Create the network and connect the controllers.
  94         # NOTE: This is quite different if using Garnet!
  95         self.network.connectControllers(self.controllers)
  96         self.network.setup_buffers()
  97
  98         # Set up a proxy port for the system_port. Used for load binaries and
  99         # other functional-only things.
 100         self.sys_port_proxy = RubyPortProxy()
 101         system.system_port = self.sys_port_proxy.slave
 102
 103         # Connect the cpu's cache, interrupt, and TLB ports to Ruby
 104         for i,cpu in enumerate(cpus):
 105             self.sequencers[i].connectCpuPorts(cpu)
 106
 107
 108 class L1Cache(L1Cache_Controller):
 109
 110     _version = 0
 111     @classmethod
 112     def versionCount(cls):
 113         cls._version += 1 # Use count for this particular type
 114         return cls._version - 1
 115
 116     def __init__(self, system, ruby_system, cpu):
 117         """CPUs are needed to grab the clock domain and system is needed for
 118            the cache block size.
 119         """
 120         super(L1Cache, self).__init__()
 121
 122         self.version = self.versionCount()
 123         # This is the cache memory object that stores the cache data and tags
 124         self.cacheMemory = RubyCache(size = '16kB',
 125                                assoc = 8,
 126                                start_index_bit = self.getBlockSizeBits(system))
 127         self.clk_domain = cpu.clk_domain
 128         self.send_evictions = self.sendEvicts(cpu)
 129         self.ruby_system = ruby_system
 130         self.connectQueues(ruby_system)
 131
 132     def getBlockSizeBits(self, system):
 133         bits = int(math.log(system.cache_line_size, 2))
 134         if 2**bits != system.cache_line_size.value:
 135             panic("Cache line size not a power of 2!")
 136         return bits
 137
 138     def sendEvicts(self, cpu):
 139         """True if the CPU model or ISA requires sending evictions from caches
 140            to the CPU. Two scenarios warrant forwarding evictions to the CPU:
 141            1. The O3 model must keep the LSQ coherent with the caches
 142            2. The x86 mwait instruction is built on top of coherence
 143            3. The local exclusive monitor in ARM systems
 144         """
 145         if type(cpu) is DerivO3CPU or \
 146            buildEnv['TARGET_ISA'] in ('x86', 'arm'):
 147             return True
 148         return False
 149
 150     def connectQueues(self, ruby_system):
 151         """Connect all of the queues for this controller.
 152         """
 153         # mandatoryQueue is a special variable. It is used by the sequencer to
 154         # send RubyRequests from the CPU (or other processor). It isn't
 155         # explicitly connected to anything.
 156         self.mandatoryQueue = MessageBuffer()
 157
 158         # All message buffers must be created and connected to the general
 159         # Ruby network. In this case, "slave/master" don't mean the same thing
 160         # as normal gem5 ports. If a MessageBuffer is a "to" buffer (i.e., out)
 161         # then you use the "master", otherwise, the slave.
 162         self.requestToDir = MessageBuffer(ordered = True)
 163         self.requestToDir.master = ruby_system.network.slave
 164         self.responseToDirOrSibling = MessageBuffer(ordered = True)
 165         self.responseToDirOrSibling.master = ruby_system.network.slave
 166         self.forwardFromDir = MessageBuffer(ordered = True)
 167         self.forwardFromDir.slave = ruby_system.network.master
 168         self.responseFromDirOrSibling = MessageBuffer(ordered = True)
 169         self.responseFromDirOrSibling.slave = ruby_system.network.master
 170
 171 class DirController(Directory_Controller):
 172
 173     _version = 0
 174     @classmethod
 175     def versionCount(cls):
 176         cls._version += 1 # Use count for this particular type
 177         return cls._version - 1
 178
 179     def __init__(self, ruby_system, ranges, mem_ctrls):
 180         """ranges are the memory ranges assigned to this controller.
 181         """
 182         if len(mem_ctrls) > 1:
 183             panic("This cache system can only be connected to one mem ctrl")
 184         super(DirController, self).__init__()
 185         self.version = self.versionCount()
 186         self.addr_ranges = ranges
 187         self.ruby_system = ruby_system
 188         self.directory = RubyDirectoryMemory()
 189         # Connect this directory to the memory side.
 190         self.memory = mem_ctrls[0].port
 191         self.connectQueues(ruby_system)
 192
 193     def connectQueues(self, ruby_system):
 194         self.requestFromCache = MessageBuffer(ordered = True)
 195         self.requestFromCache.slave = ruby_system.network.master
 196         self.responseFromCache = MessageBuffer(ordered = True)
 197         self.responseFromCache.slave = ruby_system.network.master
 198
 199         self.responseToCache = MessageBuffer(ordered = True)
 200         self.responseToCache.master = ruby_system.network.slave
 201         self.forwardToCache = MessageBuffer(ordered = True)
 202         self.forwardToCache.master = ruby_system.network.slave
 203
 204         # These are other special message buffers. They are used to send
 205         # requests to memory and responses from memory back to the controller.
 206         # Any messages sent or received on the memory port (see self.memory
 207         # above) will be directed through these message buffers.
 208         self.requestToMemory = MessageBuffer()
 209         self.responseFromMemory = MessageBuffer()
 210
 211 class MyNetwork(SimpleNetwork):
 212     """A simple point-to-point network. This doesn't not use garnet.
 213     """
 214
 215     def __init__(self, ruby_system):
 216         super(MyNetwork, self).__init__()
 217         self.netifs = []
 218         self.ruby_system = ruby_system
 219
 220     def connectControllers(self, controllers):
 221         """Connect all of the controllers to routers and connec the routers
 222            together in a point-to-point network.
 223         """
 224         # Create one router/switch per controller in the system
 225         self.routers = [Switch(router_id = i) for i in range(len(controllers))]
 226
 227         # Make a link from each controller to the router. The link goes
 228         # externally to the network.
 229         self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
 230                                         int_node=self.routers[i])
 231                           for i, c in enumerate(controllers)]
 232
 233         # Make an "internal" link (internal to the network) between every pair
 234         # of routers.
 235         link_count = 0
 236         self.int_links = []
 237         for ri in self.routers:
 238             for rj in self.routers:
 239                 if ri == rj: continue # Don't connect a router to itself!
 240                 link_count += 1
 241                 self.int_links.append(SimpleIntLink(link_id = link_count,
 242                                                     src_node = ri,
 243                                                     dst_node = rj))