configs/learning_gem5/part3/msi_caches.py

   1 # -*- coding: utf-8 -*-
   2 # Copyright (c) 2017 Jason Power
   3 # All rights reserved.
   4 #
   5 # Redistribution and use in source and binary forms, with or without
   6 # modification, are permitted provided that the following conditions are
   7 # met: redistributions of source code must retain the above copyright
   8 # notice, this list of conditions and the following disclaimer;
   9 # redistributions in binary form must reproduce the above copyright
  10 # notice, this list of conditions and the following disclaimer in the
  11 # documentation and/or other materials provided with the distribution;
  12 # neither the name of the copyright holders nor the names of its
  13 # contributors may be used to endorse or promote products derived from
  14 # this software without specific prior written permission.
  15 #
  16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27
  28 """ This file creates a set of Ruby caches, the Ruby network, and a simple
  29 point-to-point topology.
  30 See Part 3 in the Learning gem5 book:
  31 http://gem5.org/documentation/learning_gem5/part3/MSIintro
  32
  33 IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
  34            also needs to be updated. For now, email Jason <jason@lowepower.com>
  35
  36 """
  37
  38 from __future__ import print_function
  39 from __future__ import absolute_import
  40
  41 import math
  42
  43 from m5.defines import buildEnv
  44 from m5.util import fatal, panic
  45
  46 from m5.objects import *
  47
  48 class MyCacheSystem(RubySystem):
  49
  50     def __init__(self):
  51         if buildEnv['PROTOCOL'] != 'MSI':
  52             fatal("This system assumes MSI from learning gem5!")
  53
  54         super(MyCacheSystem, self).__init__()
  55
  56     def setup(self, system, cpus, mem_ctrls):
  57         """Set up the Ruby cache subsystem. Note: This can't be done in the
  58            constructor because many of these items require a pointer to the
  59            ruby system (self). This causes infinite recursion in initialize()
  60            if we do this in the __init__.
  61         """
  62         # Ruby's global network.
  63         self.network = MyNetwork(self)
  64
  65         # MSI uses 3 virtual networks. One for requests (lowest priority), one
  66         # for responses (highest priority), and one for "forwards" or
  67         # cache-to-cache requests. See *.sm files for details.
  68         self.number_of_virtual_networks = 3
  69         self.network.number_of_virtual_networks = 3
  70
  71         # There is a single global list of all of the controllers to make it
  72         # easier to connect everything to the global network. This can be
  73         # customized depending on the topology/network requirements.
  74         # Create one controller for each L1 cache (and the cache mem obj.)
  75         # Create a single directory controller (Really the memory cntrl)
  76         self.controllers = \
  77             [L1Cache(system, self, cpu) for cpu in cpus] + \
  78             [DirController(self, system.mem_ranges, mem_ctrls)]
  79
  80         # Create one sequencer per CPU. In many systems this is more
  81         # complicated since you have to create sequencers for DMA controllers
  82         # and other controllers, too.
  83         self.sequencers = [RubySequencer(version = i,
  84                                 # I/D cache is combined and grab from ctrl
  85                                 dcache = self.controllers[i].cacheMemory,
  86                                 clk_domain = self.controllers[i].clk_domain,
  87                                 ) for i in range(len(cpus))]
  88
  89         # We know that we put the controllers in an order such that the first
  90         # N of them are the L1 caches which need a sequencer pointer
  91         for i,c in enumerate(self.controllers[0:len(self.sequencers)]):
  92             c.sequencer = self.sequencers[i]
  93
  94         self.num_of_sequencers = len(self.sequencers)
  95
  96         # Create the network and connect the controllers.
  97         # NOTE: This is quite different if using Garnet!
  98         self.network.connectControllers(self.controllers)
  99         self.network.setup_buffers()
 100
 101         # Set up a proxy port for the system_port. Used for load binaries and
 102         # other functional-only things.
 103         self.sys_port_proxy = RubyPortProxy()
 104         system.system_port = self.sys_port_proxy.slave
 105
 106         # Connect the cpu's cache, interrupt, and TLB ports to Ruby
 107         for i,cpu in enumerate(cpus):
 108             cpu.icache_port = self.sequencers[i].slave
 109             cpu.dcache_port = self.sequencers[i].slave
 110             isa = buildEnv['TARGET_ISA']
 111             if isa == 'x86':
 112                 cpu.interrupts[0].pio = self.sequencers[i].master
 113                 cpu.interrupts[0].int_master = self.sequencers[i].slave
 114                 cpu.interrupts[0].int_slave = self.sequencers[i].master
 115             if isa == 'x86' or isa == 'arm':
 116                 cpu.itb.walker.port = self.sequencers[i].slave
 117                 cpu.dtb.walker.port = self.sequencers[i].slave
 118
 119
 120 class L1Cache(L1Cache_Controller):
 121
 122     _version = 0
 123     @classmethod
 124     def versionCount(cls):
 125         cls._version += 1 # Use count for this particular type
 126         return cls._version - 1
 127
 128     def __init__(self, system, ruby_system, cpu):
 129         """CPUs are needed to grab the clock domain and system is needed for
 130            the cache block size.
 131         """
 132         super(L1Cache, self).__init__()
 133
 134         self.version = self.versionCount()
 135         # This is the cache memory object that stores the cache data and tags
 136         self.cacheMemory = RubyCache(size = '16kB',
 137                                assoc = 8,
 138                                start_index_bit = self.getBlockSizeBits(system))
 139         self.clk_domain = cpu.clk_domain
 140         self.send_evictions = self.sendEvicts(cpu)
 141         self.ruby_system = ruby_system
 142         self.connectQueues(ruby_system)
 143
 144     def getBlockSizeBits(self, system):
 145         bits = int(math.log(system.cache_line_size, 2))
 146         if 2**bits != system.cache_line_size.value:
 147             panic("Cache line size not a power of 2!")
 148         return bits
 149
 150     def sendEvicts(self, cpu):
 151         """True if the CPU model or ISA requires sending evictions from caches
 152            to the CPU. Two scenarios warrant forwarding evictions to the CPU:
 153            1. The O3 model must keep the LSQ coherent with the caches
 154            2. The x86 mwait instruction is built on top of coherence
 155            3. The local exclusive monitor in ARM systems
 156         """
 157         if type(cpu) is DerivO3CPU or \
 158            buildEnv['TARGET_ISA'] in ('x86', 'arm'):
 159             return True
 160         return False
 161
 162     def connectQueues(self, ruby_system):
 163         """Connect all of the queues for this controller.
 164         """
 165         # mandatoryQueue is a special variable. It is used by the sequencer to
 166         # send RubyRequests from the CPU (or other processor). It isn't
 167         # explicitly connected to anything.
 168         self.mandatoryQueue = MessageBuffer()
 169
 170         # All message buffers must be created and connected to the general
 171         # Ruby network. In this case, "slave/master" don't mean the same thing
 172         # as normal gem5 ports. If a MessageBuffer is a "to" buffer (i.e., out)
 173         # then you use the "master", otherwise, the slave.
 174         self.requestToDir = MessageBuffer(ordered = True)
 175         self.requestToDir.master = ruby_system.network.slave
 176         self.responseToDirOrSibling = MessageBuffer(ordered = True)
 177         self.responseToDirOrSibling.master = ruby_system.network.slave
 178         self.forwardFromDir = MessageBuffer(ordered = True)
 179         self.forwardFromDir.slave = ruby_system.network.master
 180         self.responseFromDirOrSibling = MessageBuffer(ordered = True)
 181         self.responseFromDirOrSibling.slave = ruby_system.network.master
 182
 183 class DirController(Directory_Controller):
 184
 185     _version = 0
 186     @classmethod
 187     def versionCount(cls):
 188         cls._version += 1 # Use count for this particular type
 189         return cls._version - 1
 190
 191     def __init__(self, ruby_system, ranges, mem_ctrls):
 192         """ranges are the memory ranges assigned to this controller.
 193         """
 194         if len(mem_ctrls) > 1:
 195             panic("This cache system can only be connected to one mem ctrl")
 196         super(DirController, self).__init__()
 197         self.version = self.versionCount()
 198         self.addr_ranges = ranges
 199         self.ruby_system = ruby_system
 200         self.directory = RubyDirectoryMemory()
 201         # Connect this directory to the memory side.
 202         self.memory = mem_ctrls[0].port
 203         self.connectQueues(ruby_system)
 204
 205     def connectQueues(self, ruby_system):
 206         self.requestFromCache = MessageBuffer(ordered = True)
 207         self.requestFromCache.slave = ruby_system.network.master
 208         self.responseFromCache = MessageBuffer(ordered = True)
 209         self.responseFromCache.slave = ruby_system.network.master
 210
 211         self.responseToCache = MessageBuffer(ordered = True)
 212         self.responseToCache.master = ruby_system.network.slave
 213         self.forwardToCache = MessageBuffer(ordered = True)
 214         self.forwardToCache.master = ruby_system.network.slave
 215
 216         # These are other special message buffers. They are used to send
 217         # requests to memory and responses from memory back to the controller.
 218         # Any messages sent or received on the memory port (see self.memory
 219         # above) will be directed through these message buffers.
 220         self.requestToMemory = MessageBuffer()
 221         self.responseFromMemory = MessageBuffer()
 222
 223 class MyNetwork(SimpleNetwork):
 224     """A simple point-to-point network. This doesn't not use garnet.
 225     """
 226
 227     def __init__(self, ruby_system):
 228         super(MyNetwork, self).__init__()
 229         self.netifs = []
 230         self.ruby_system = ruby_system
 231
 232     def connectControllers(self, controllers):
 233         """Connect all of the controllers to routers and connec the routers
 234            together in a point-to-point network.
 235         """
 236         # Create one router/switch per controller in the system
 237         self.routers = [Switch(router_id = i) for i in range(len(controllers))]
 238
 239         # Make a link from each controller to the router. The link goes
 240         # externally to the network.
 241         self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
 242                                         int_node=self.routers[i])
 243                           for i, c in enumerate(controllers)]
 244
 245         # Make an "internal" link (internal to the network) between every pair
 246         # of routers.
 247         link_count = 0
 248         self.int_links = []
 249         for ri in self.routers:
 250             for rj in self.routers:
 251                 if ri == rj: continue # Don't connect a router to itself!
 252                 link_count += 1
 253                 self.int_links.append(SimpleIntLink(link_id = link_count,
 254                                                     src_node = ri,
 255                                                     dst_node = rj))