configs/learning_gem5/part3/msi_caches.py

   1 # -*- coding: utf-8 -*-
   2 # Copyright (c) 2017 Jason Power
   3 # All rights reserved.
   4 #
   5 # Redistribution and use in source and binary forms, with or without
   6 # modification, are permitted provided that the following conditions are
   7 # met: redistributions of source code must retain the above copyright
   8 # notice, this list of conditions and the following disclaimer;
   9 # redistributions in binary form must reproduce the above copyright
  10 # notice, this list of conditions and the following disclaimer in the
  11 # documentation and/or other materials provided with the distribution;
  12 # neither the name of the copyright holders nor the names of its
  13 # contributors may be used to endorse or promote products derived from
  14 # this software without specific prior written permission.
  15 #
  16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27
  28 """ This file creates a set of Ruby caches, the Ruby network, and a simple
  29 point-to-point topology.
  30 See Part 3 in the Learning gem5 book:
  31 http://gem5.org/documentation/learning_gem5/part3/MSIintro
  32
  33 IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
  34            also needs to be updated. For now, email Jason <jason@lowepower.com>
  35
  36 """
  37
  38 from __future__ import print_function
  39 from __future__ import absolute_import
  40
  41 import math
  42
  43 from m5.defines import buildEnv
  44 from m5.util import fatal, panic
  45
  46 from m5.objects import *
  47
  48 class MyCacheSystem(RubySystem):
  49
  50     def __init__(self):
  51         if buildEnv['PROTOCOL'] != 'MSI':
  52             fatal("This system assumes MSI from learning gem5!")
  53
  54         super(MyCacheSystem, self).__init__()
  55
  56     def setup(self, system, cpus, mem_ctrls):
  57         """Set up the Ruby cache subsystem. Note: This can't be done in the
  58            constructor because many of these items require a pointer to the
  59            ruby system (self). This causes infinite recursion in initialize()
  60            if we do this in the __init__.
  61         """
  62         # Ruby's global network.
  63         self.network = MyNetwork(self)
  64
  65         # MSI uses 3 virtual networks. One for requests (lowest priority), one
  66         # for responses (highest priority), and one for "forwards" or
  67         # cache-to-cache requests. See *.sm files for details.
  68         self.number_of_virtual_networks = 3
  69         self.network.number_of_virtual_networks = 3
  70
  71         # There is a single global list of all of the controllers to make it
  72         # easier to connect everything to the global network. This can be
  73         # customized depending on the topology/network requirements.
  74         # Create one controller for each L1 cache (and the cache mem obj.)
  75         # Create a single directory controller (Really the memory cntrl)
  76         self.controllers = \
  77             [L1Cache(system, self, cpu) for cpu in cpus] + \
  78             [DirController(self, system.mem_ranges, mem_ctrls)]
  79
  80         # Create one sequencer per CPU. In many systems this is more
  81         # complicated since you have to create sequencers for DMA controllers
  82         # and other controllers, too.
  83         self.sequencers = [RubySequencer(version = i,
  84                                 # I/D cache is combined and grab from ctrl
  85                                 icache = self.controllers[i].cacheMemory,
  86                                 dcache = self.controllers[i].cacheMemory,
  87                                 clk_domain = self.controllers[i].clk_domain,
  88                                 ) for i in range(len(cpus))]
  89
  90         # We know that we put the controllers in an order such that the first
  91         # N of them are the L1 caches which need a sequencer pointer
  92         for i,c in enumerate(self.controllers[0:len(self.sequencers)]):
  93             c.sequencer = self.sequencers[i]
  94
  95         self.num_of_sequencers = len(self.sequencers)
  96
  97         # Create the network and connect the controllers.
  98         # NOTE: This is quite different if using Garnet!
  99         self.network.connectControllers(self.controllers)
 100         self.network.setup_buffers()
 101
 102         # Set up a proxy port for the system_port. Used for load binaries and
 103         # other functional-only things.
 104         self.sys_port_proxy = RubyPortProxy()
 105         system.system_port = self.sys_port_proxy.slave
 106
 107         # Connect the cpu's cache, interrupt, and TLB ports to Ruby
 108         for i,cpu in enumerate(cpus):
 109             cpu.icache_port = self.sequencers[i].slave
 110             cpu.dcache_port = self.sequencers[i].slave
 111             isa = buildEnv['TARGET_ISA']
 112             if isa == 'x86':
 113                 cpu.interrupts[0].pio = self.sequencers[i].master
 114                 cpu.interrupts[0].int_master = self.sequencers[i].slave
 115                 cpu.interrupts[0].int_slave = self.sequencers[i].master
 116             if isa == 'x86' or isa == 'arm':
 117                 cpu.itb.walker.port = self.sequencers[i].slave
 118                 cpu.dtb.walker.port = self.sequencers[i].slave
 119
 120
 121 class L1Cache(L1Cache_Controller):
 122
 123     _version = 0
 124     @classmethod
 125     def versionCount(cls):
 126         cls._version += 1 # Use count for this particular type
 127         return cls._version - 1
 128
 129     def __init__(self, system, ruby_system, cpu):
 130         """CPUs are needed to grab the clock domain and system is needed for
 131            the cache block size.
 132         """
 133         super(L1Cache, self).__init__()
 134
 135         self.version = self.versionCount()
 136         # This is the cache memory object that stores the cache data and tags
 137         self.cacheMemory = RubyCache(size = '16kB',
 138                                assoc = 8,
 139                                start_index_bit = self.getBlockSizeBits(system))
 140         self.clk_domain = cpu.clk_domain
 141         self.send_evictions = self.sendEvicts(cpu)
 142         self.ruby_system = ruby_system
 143         self.connectQueues(ruby_system)
 144
 145     def getBlockSizeBits(self, system):
 146         bits = int(math.log(system.cache_line_size, 2))
 147         if 2**bits != system.cache_line_size.value:
 148             panic("Cache line size not a power of 2!")
 149         return bits
 150
 151     def sendEvicts(self, cpu):
 152         """True if the CPU model or ISA requires sending evictions from caches
 153            to the CPU. Two scenarios warrant forwarding evictions to the CPU:
 154            1. The O3 model must keep the LSQ coherent with the caches
 155            2. The x86 mwait instruction is built on top of coherence
 156            3. The local exclusive monitor in ARM systems
 157         """
 158         if type(cpu) is DerivO3CPU or \
 159            buildEnv['TARGET_ISA'] in ('x86', 'arm'):
 160             return True
 161         return False
 162
 163     def connectQueues(self, ruby_system):
 164         """Connect all of the queues for this controller.
 165         """
 166         # mandatoryQueue is a special variable. It is used by the sequencer to
 167         # send RubyRequests from the CPU (or other processor). It isn't
 168         # explicitly connected to anything.
 169         self.mandatoryQueue = MessageBuffer()
 170
 171         # All message buffers must be created and connected to the general
 172         # Ruby network. In this case, "slave/master" don't mean the same thing
 173         # as normal gem5 ports. If a MessageBuffer is a "to" buffer (i.e., out)
 174         # then you use the "master", otherwise, the slave.
 175         self.requestToDir = MessageBuffer(ordered = True)
 176         self.requestToDir.master = ruby_system.network.slave
 177         self.responseToDirOrSibling = MessageBuffer(ordered = True)
 178         self.responseToDirOrSibling.master = ruby_system.network.slave
 179         self.forwardFromDir = MessageBuffer(ordered = True)
 180         self.forwardFromDir.slave = ruby_system.network.master
 181         self.responseFromDirOrSibling = MessageBuffer(ordered = True)
 182         self.responseFromDirOrSibling.slave = ruby_system.network.master
 183
 184 class DirController(Directory_Controller):
 185
 186     _version = 0
 187     @classmethod
 188     def versionCount(cls):
 189         cls._version += 1 # Use count for this particular type
 190         return cls._version - 1
 191
 192     def __init__(self, ruby_system, ranges, mem_ctrls):
 193         """ranges are the memory ranges assigned to this controller.
 194         """
 195         if len(mem_ctrls) > 1:
 196             panic("This cache system can only be connected to one mem ctrl")
 197         super(DirController, self).__init__()
 198         self.version = self.versionCount()
 199         self.addr_ranges = ranges
 200         self.ruby_system = ruby_system
 201         self.directory = RubyDirectoryMemory()
 202         # Connect this directory to the memory side.
 203         self.memory = mem_ctrls[0].port
 204         self.connectQueues(ruby_system)
 205
 206     def connectQueues(self, ruby_system):
 207         self.requestFromCache = MessageBuffer(ordered = True)
 208         self.requestFromCache.slave = ruby_system.network.master
 209         self.responseFromCache = MessageBuffer(ordered = True)
 210         self.responseFromCache.slave = ruby_system.network.master
 211
 212         self.responseToCache = MessageBuffer(ordered = True)
 213         self.responseToCache.master = ruby_system.network.slave
 214         self.forwardToCache = MessageBuffer(ordered = True)
 215         self.forwardToCache.master = ruby_system.network.slave
 216
 217         # These are other special message buffers. They are used to send
 218         # requests to memory and responses from memory back to the controller.
 219         # Any messages sent or received on the memory port (see self.memory
 220         # above) will be directed through these message buffers.
 221         self.requestToMemory = MessageBuffer()
 222         self.responseFromMemory = MessageBuffer()
 223
 224 class MyNetwork(SimpleNetwork):
 225     """A simple point-to-point network. This doesn't not use garnet.
 226     """
 227
 228     def __init__(self, ruby_system):
 229         super(MyNetwork, self).__init__()
 230         self.netifs = []
 231         self.ruby_system = ruby_system
 232
 233     def connectControllers(self, controllers):
 234         """Connect all of the controllers to routers and connec the routers
 235            together in a point-to-point network.
 236         """
 237         # Create one router/switch per controller in the system
 238         self.routers = [Switch(router_id = i) for i in range(len(controllers))]
 239
 240         # Make a link from each controller to the router. The link goes
 241         # externally to the network.
 242         self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
 243                                         int_node=self.routers[i])
 244                           for i, c in enumerate(controllers)]
 245
 246         # Make an "internal" link (internal to the network) between every pair
 247         # of routers.
 248         link_count = 0
 249         self.int_links = []
 250         for ri in self.routers:
 251             for rj in self.routers:
 252                 if ri == rj: continue # Don't connect a router to itself!
 253                 link_count += 1
 254                 self.int_links.append(SimpleIntLink(link_id = link_count,
 255                                                     src_node = ri,
 256                                                     dst_node = rj))