configs/learning_gem5/part3/ruby_caches_MI_example.py

   1 # -*- coding: utf-8 -*-
   2 # Copyright (c) 2015 Jason Power
   3 # All rights reserved.
   4 #
   5 # Redistribution and use in source and binary forms, with or without
   6 # modification, are permitted provided that the following conditions are
   7 # met: redistributions of source code must retain the above copyright
   8 # notice, this list of conditions and the following disclaimer;
   9 # redistributions in binary form must reproduce the above copyright
  10 # notice, this list of conditions and the following disclaimer in the
  11 # documentation and/or other materials provided with the distribution;
  12 # neither the name of the copyright holders nor the names of its
  13 # contributors may be used to endorse or promote products derived from
  14 # this software without specific prior written permission.
  15 #
  16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27
  28 """ This file creates a set of Ruby caches, the Ruby network, and a simple
  29 point-to-point topology.
  30 See Part 3 in the Learning gem5 book:
  31 http://gem5.org/Documentation/learning_gem5/part3/MSIintro
  32 You can change simple_ruby to import from this file instead of from msi_caches
  33 to use the MI_example protocol instead of MSI.
  34
  35 IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
  36            also needs to be updated. For now, email Jason <jason@lowepower.com>
  37
  38 """
  39
  40 from __future__ import print_function
  41 from __future__ import absolute_import
  42
  43 import math
  44
  45 from m5.defines import buildEnv
  46 from m5.util import fatal, panic
  47
  48 from m5.objects import *
  49
  50 class MyCacheSystem(RubySystem):
  51
  52     def __init__(self):
  53         if buildEnv['PROTOCOL'] != 'MI_example':
  54             fatal("This system assumes MI_example!")
  55
  56         super(MyCacheSystem, self).__init__()
  57
  58     def setup(self, system, cpus, mem_ctrls):
  59         """Set up the Ruby cache subsystem. Note: This can't be done in the
  60            constructor because many of these items require a pointer to the
  61            ruby system (self). This causes infinite recursion in initialize()
  62            if we do this in the __init__.
  63         """
  64         # Ruby's global network.
  65         self.network = MyNetwork(self)
  66
  67         # MI example uses 5 virtual networks
  68         self.number_of_virtual_networks = 5
  69         self.network.number_of_virtual_networks = 5
  70
  71         # There is a single global list of all of the controllers to make it
  72         # easier to connect everything to the global network. This can be
  73         # customized depending on the topology/network requirements.
  74         # Create one controller for each L1 cache (and the cache mem obj.)
  75         # Create a single directory controller (Really the memory cntrl)
  76         self.controllers = \
  77             [L1Cache(system, self, cpu) for cpu in cpus] + \
  78             [DirController(self, system.mem_ranges, mem_ctrls)]
  79
  80         # Create one sequencer per CPU. In many systems this is more
  81         # complicated since you have to create sequencers for DMA controllers
  82         # and other controllers, too.
  83         self.sequencers = [RubySequencer(version = i,
  84                                 # I/D cache is combined and grab from ctrl
  85                                 icache = self.controllers[i].cacheMemory,
  86                                 dcache = self.controllers[i].cacheMemory,
  87                                 clk_domain = self.controllers[i].clk_domain,
  88                                 ) for i in range(len(cpus))]
  89
  90         for i,c in enumerate(self.controllers[0:len(cpus)]):
  91             c.sequencer = self.sequencers[i]
  92
  93         self.num_of_sequencers = len(self.sequencers)
  94
  95         # Create the network and connect the controllers.
  96         # NOTE: This is quite different if using Garnet!
  97         self.network.connectControllers(self.controllers)
  98         self.network.setup_buffers()
  99
 100         # Set up a proxy port for the system_port. Used for load binaries and
 101         # other functional-only things.
 102         self.sys_port_proxy = RubyPortProxy()
 103         system.system_port = self.sys_port_proxy.slave
 104
 105         # Connect the cpu's cache, interrupt, and TLB ports to Ruby
 106         for i,cpu in enumerate(cpus):
 107             cpu.icache_port = self.sequencers[i].slave
 108             cpu.dcache_port = self.sequencers[i].slave
 109             isa = buildEnv['TARGET_ISA']
 110             if isa == 'x86':
 111                 cpu.interrupts[0].pio = self.sequencers[i].master
 112                 cpu.interrupts[0].int_master = self.sequencers[i].slave
 113                 cpu.interrupts[0].int_slave = self.sequencers[i].master
 114             if isa == 'x86' or isa == 'arm':
 115                 cpu.itb.walker.port = self.sequencers[i].slave
 116                 cpu.dtb.walker.port = self.sequencers[i].slave
 117
 118 class L1Cache(L1Cache_Controller):
 119
 120     _version = 0
 121     @classmethod
 122     def versionCount(cls):
 123         cls._version += 1 # Use count for this particular type
 124         return cls._version - 1
 125
 126     def __init__(self, system, ruby_system, cpu):
 127         """CPUs are needed to grab the clock domain and system is needed for
 128            the cache block size.
 129         """
 130         super(L1Cache, self).__init__()
 131
 132         self.version = self.versionCount()
 133         # This is the cache memory object that stores the cache data and tags
 134         self.cacheMemory = RubyCache(size = '16kB',
 135                                assoc = 8,
 136                                start_index_bit = self.getBlockSizeBits(system))
 137         self.clk_domain = cpu.clk_domain
 138         self.send_evictions = self.sendEvicts(cpu)
 139         self.ruby_system = ruby_system
 140         self.connectQueues(ruby_system)
 141
 142     def getBlockSizeBits(self, system):
 143         bits = int(math.log(system.cache_line_size, 2))
 144         if 2**bits != system.cache_line_size.value:
 145             panic("Cache line size not a power of 2!")
 146         return bits
 147
 148     def sendEvicts(self, cpu):
 149         """True if the CPU model or ISA requires sending evictions from caches
 150            to the CPU. Two scenarios warrant forwarding evictions to the CPU:
 151            1. The O3 model must keep the LSQ coherent with the caches
 152            2. The x86 mwait instruction is built on top of coherence
 153            3. The local exclusive monitor in ARM systems
 154         """
 155         if type(cpu) is DerivO3CPU or \
 156            buildEnv['TARGET_ISA'] in ('x86', 'arm'):
 157             return True
 158         return False
 159
 160     def connectQueues(self, ruby_system):
 161         """Connect all of the queues for this controller.
 162         """
 163         self.mandatoryQueue = MessageBuffer()
 164         self.requestFromCache = MessageBuffer(ordered = True)
 165         self.requestFromCache.master = ruby_system.network.slave
 166         self.responseFromCache = MessageBuffer(ordered = True)
 167         self.responseFromCache.master = ruby_system.network.slave
 168         self.forwardToCache = MessageBuffer(ordered = True)
 169         self.forwardToCache.slave = ruby_system.network.master
 170         self.responseToCache = MessageBuffer(ordered = True)
 171         self.responseToCache.slave = ruby_system.network.master
 172
 173 class DirController(Directory_Controller):
 174
 175     _version = 0
 176     @classmethod
 177     def versionCount(cls):
 178         cls._version += 1 # Use count for this particular type
 179         return cls._version - 1
 180
 181     def __init__(self, ruby_system, ranges, mem_ctrls):
 182         """ranges are the memory ranges assigned to this controller.
 183         """
 184         if len(mem_ctrls) > 1:
 185             panic("This cache system can only be connected to one mem ctrl")
 186         super(DirController, self).__init__()
 187         self.version = self.versionCount()
 188         self.addr_ranges = ranges
 189         self.ruby_system = ruby_system
 190         self.directory = RubyDirectoryMemory()
 191         # Connect this directory to the memory side.
 192         self.memory = mem_ctrls[0].port
 193         self.connectQueues(ruby_system)
 194
 195     def connectQueues(self, ruby_system):
 196         self.requestToDir = MessageBuffer(ordered = True)
 197         self.requestToDir.slave = ruby_system.network.master
 198         self.dmaRequestToDir = MessageBuffer(ordered = True)
 199         self.dmaRequestToDir.slave = ruby_system.network.master
 200
 201         self.responseFromDir = MessageBuffer()
 202         self.responseFromDir.master = ruby_system.network.slave
 203         self.dmaResponseFromDir = MessageBuffer(ordered = True)
 204         self.dmaResponseFromDir.master = ruby_system.network.slave
 205         self.forwardFromDir = MessageBuffer()
 206         self.forwardFromDir.master = ruby_system.network.slave
 207         self.requestToMemory = MessageBuffer()
 208         self.responseFromMemory = MessageBuffer()
 209
 210 class MyNetwork(SimpleNetwork):
 211     """A simple point-to-point network. This doesn't not use garnet.
 212     """
 213
 214     def __init__(self, ruby_system):
 215         super(MyNetwork, self).__init__()
 216         self.netifs = []
 217         self.ruby_system = ruby_system
 218
 219     def connectControllers(self, controllers):
 220         """Connect all of the controllers to routers and connec the routers
 221            together in a point-to-point network.
 222         """
 223         # Create one router/switch per controller in the system
 224         self.routers = [Switch(router_id = i) for i in range(len(controllers))]
 225
 226         # Make a link from each controller to the router. The link goes
 227         # externally to the network.
 228         self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
 229                                         int_node=self.routers[i])
 230                           for i, c in enumerate(controllers)]
 231
 232         # Make an "internal" link (internal to the network) between every pair
 233         # of routers.
 234         link_count = 0
 235         self.int_links = []
 236         for ri in self.routers:
 237             for rj in self.routers:
 238                 if ri == rj: continue # Don't connect a router to itself!
 239                 link_count += 1
 240                 self.int_links.append(SimpleIntLink(link_id = link_count,
 241                                                     src_node = ri,
 242                                                     dst_node = rj))