7e0bd9e7fa523a3c7ae42b36747cbd1f97b1bcee
1 # Copyright (c) 2020 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
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11 # modified or unmodified, in source code or in binary form.
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15 # met: redistributions of source code must retain the above copyright
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22 # this software without specific prior written permission.
24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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28 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 # Authors: Andreas Hansson
38 from __future__
import print_function
39 from __future__
import absolute_import
45 from m5
.objects
import *
46 from m5
.util
import addToPath
47 from m5
.stats
import periodicStatDump
51 from common
import ObjectList
52 from common
import MemConfig
54 # this script is helpful to sweep the efficiency of a specific memory
55 # controller configuration, by varying the number of banks accessed,
56 # and the sequential stride size (how many bytes per activate), and
57 # observe what bus utilisation (bandwidth) is achieved
59 parser
= optparse
.OptionParser()
62 "NVM" : lambda x
: x
.createNvm
,
65 # Use a single-channel DDR3-1600 x64 (8x8 topology) by default
66 parser
.add_option("--nvm-type", type="choice", default
="NVM_2400_1x64",
67 choices
=ObjectList
.mem_list
.get_names(),
68 help = "type of memory to use")
70 parser
.add_option("--nvm-ranks", "-r", type="int", default
=1,
71 help = "Number of ranks to iterate across")
73 parser
.add_option("--rd_perc", type="int", default
=100,
74 help = "Percentage of read commands")
76 parser
.add_option("--mode", type="choice", default
="NVM",
77 choices
=nvm_generators
.keys(),
78 help = "NVM: Random traffic")
80 parser
.add_option("--addr-map", type="choice",
81 choices
=ObjectList
.dram_addr_map_list
.get_names(),
82 default
="RoRaBaCoCh", help = "NVM address map policy")
84 (options
, args
) = parser
.parse_args()
87 print("Error: script doesn't take any positional arguments")
90 # at the moment we stay with the default open-adaptive page policy,
93 # start with the system itself, using a multi-layer 2.0 GHz
94 # crossbar, delivering 64 bytes / 3 cycles (one header cycle)
95 # which amounts to 42.7 GByte/s per layer and thus per port
96 system
= System(membus
= IOXBar(width
= 32))
97 system
.clk_domain
= SrcClockDomain(clock
= '2.0GHz',
99 VoltageDomain(voltage
= '1V'))
101 # we are fine with 256 MB memory for now
102 mem_range
= AddrRange('512MB')
103 system
.mem_ranges
= [mem_range
]
105 # do not worry about reserving space for the backing store
106 system
.mmap_using_noreserve
= True
108 # force a single channel to match the assumptions in the DRAM traffic
110 options
.mem_channels
= 1
111 options
.external_memory_system
= 0
112 MemConfig
.config_mem(options
, system
)
114 # the following assumes that we are using the native memory
115 # controller with an NVM interface, check to be sure
116 if not isinstance(system
.mem_ctrls
[0], m5
.objects
.MemCtrl
):
117 fatal("This script assumes the controller is a MemCtrl subclass")
118 if not isinstance(system
.mem_ctrls
[0].nvm
, m5
.objects
.NVMInterface
):
119 fatal("This script assumes the memory is a NVMInterface class")
121 # there is no point slowing things down by saving any data
122 system
.mem_ctrls
[0].nvm
.null
= True
124 # Set the address mapping based on input argument
125 system
.mem_ctrls
[0].nvm
.addr_mapping
= options
.addr_map
127 # stay in each state for 0.25 ms, long enough to warm things up, and
128 # short enough to avoid hitting a refresh
131 # stay in each state as long as the dump/reset period, use the entire
132 # range, issue transactions of the right DRAM burst size, and match
133 # the DRAM maximum bandwidth to ensure that it is saturated
135 # get the number of regions
136 nbr_banks
= system
.mem_ctrls
[0].nvm
.banks_per_rank
.value
138 # determine the burst length in bytes
139 burst_size
= int((system
.mem_ctrls
[0].nvm
.devices_per_rank
.value
*
140 system
.mem_ctrls
[0].nvm
.device_bus_width
.value
*
141 system
.mem_ctrls
[0].nvm
.burst_length
.value
) / 8)
144 # next, get the page size in bytes
145 buffer_size
= system
.mem_ctrls
[0].nvm
.devices_per_rank
.value
* \
146 system
.mem_ctrls
[0].nvm
.device_rowbuffer_size
.value
148 # match the maximum bandwidth of the memory, the parameter is in seconds
149 # and we need it in ticks (ps)
150 itt
= system
.mem_ctrls
[0].nvm
.tBURST
.value
* 1000000000000
152 # assume we start at 0
153 max_addr
= mem_range
.end
155 # use min of the page size and 512 bytes as that should be more than
157 max_stride
= min(256, buffer_size
)
159 # create a traffic generator, and point it to the file we just created
160 system
.tgen
= PyTrafficGen()
162 # add a communication monitor
163 system
.monitor
= CommMonitor()
165 # connect the traffic generator to the bus via a communication monitor
166 system
.tgen
.port
= system
.monitor
.slave
167 system
.monitor
.master
= system
.membus
.slave
169 # connect the system port even if it is not used in this example
170 system
.system_port
= system
.membus
.slave
172 # every period, dump and reset all stats
173 periodicStatDump(period
)
176 root
= Root(full_system
= False, system
= system
)
177 root
.system
.mem_mode
= 'timing'
182 addr_map
= ObjectList
.dram_addr_map_list
.get(options
.addr_map
)
183 generator
= nvm_generators
[options
.mode
](system
.tgen
)
184 for stride_size
in range(burst_size
, max_stride
+ 1, burst_size
):
185 for bank
in range(1, nbr_banks
+ 1):
186 num_seq_pkts
= int(math
.ceil(float(stride_size
) / burst_size
))
187 yield generator(period
,
188 0, max_addr
, burst_size
, int(itt
), int(itt
),
190 num_seq_pkts
, buffer_size
, nbr_banks
, bank
,
191 addr_map
, options
.nvm_ranks
)
192 yield system
.tgen
.createExit(0)
194 system
.tgen
.start(trace())
198 print("NVM sweep with burst: %d, banks: %d, max stride: %d" %
199 (burst_size
, nbr_banks
, max_stride
))