6ba5547f988a7b711fe6c4247ca7206ee893160b
1 # Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
4 # For use for simulation and test purposes only
6 # Redistribution and use in source and binary forms, with or without
7 # modification, are permitted provided that the following conditions are met:
9 # 1. Redistributions of source code must retain the above copyright notice,
10 # this list of conditions and the following disclaimer.
12 # 2. Redistributions in binary form must reproduce the above copyright notice,
13 # this list of conditions and the following disclaimer in the documentation
14 # and/or other materials provided with the distribution.
16 # 3. Neither the name of the copyright holder nor the names of its
17 # contributors may be used to endorse or promote products derived from this
18 # software without specific prior written permission.
20 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
24 # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 # POSSIBILITY OF SUCH DAMAGE.
32 # Authors: Sooraj Puthoor,
37 from m5
.objects
import *
38 from m5
.defines
import buildEnv
39 from m5
.util
import addToPath
, convert
40 from CntrlBase
import *
44 from topologies
.Cluster
import Cluster
47 # Note: the L1 Cache latency is only used by the sequencer on fast path hits
49 class L1Cache(RubyCache
):
51 resourceStalls
= False
52 def create(self
, size
, assoc
, options
):
53 self
.size
= MemorySize(size
)
55 self
.replacement_policy
= TreePLRURP()
58 # Note: the L2 Cache latency is not currently used
60 class L2Cache(RubyCache
):
62 resourceStalls
= False
63 def create(self
, size
, assoc
, options
):
64 self
.size
= MemorySize(size
)
66 self
.replacement_policy
= TreePLRURP()
67 class CPCntrl(AMD_Base_Controller
, CntrlBase
):
69 def create(self
, options
, ruby_system
, system
):
70 self
.version
= self
.versionCount()
71 self
.cntrl_id
= self
.cntrlCount()
73 self
.L1Icache
= L1Cache()
74 self
.L1Icache
.create(options
.l1i_size
, options
.l1i_assoc
, options
)
75 self
.L1D0cache
= L1Cache()
76 self
.L1D0cache
.create(options
.l1d_size
, options
.l1d_assoc
, options
)
77 self
.L1D1cache
= L1Cache()
78 self
.L1D1cache
.create(options
.l1d_size
, options
.l1d_assoc
, options
)
79 self
.L2cache
= L2Cache()
80 self
.L2cache
.create(options
.l2_size
, options
.l2_assoc
, options
)
82 self
.sequencer
= RubySequencer()
83 self
.sequencer
.version
= self
.seqCount()
84 self
.sequencer
.icache
= self
.L1Icache
85 self
.sequencer
.dcache
= self
.L1D0cache
86 self
.sequencer
.ruby_system
= ruby_system
87 self
.sequencer
.coreid
= 0
88 self
.sequencer
.is_cpu_sequencer
= True
90 self
.sequencer1
= RubySequencer()
91 self
.sequencer1
.version
= self
.seqCount()
92 self
.sequencer1
.icache
= self
.L1Icache
93 self
.sequencer1
.dcache
= self
.L1D1cache
94 self
.sequencer1
.ruby_system
= ruby_system
95 self
.sequencer1
.coreid
= 1
96 self
.sequencer1
.is_cpu_sequencer
= True
98 self
.issue_latency
= options
.cpu_to_dir_latency
99 self
.send_evictions
= send_evicts(options
)
101 self
.ruby_system
= ruby_system
103 if options
.recycle_latency
:
104 self
.recycle_latency
= options
.recycle_latency
106 def define_options(parser
):
107 parser
.add_option("--cpu-to-dir-latency", type="int", default
=15)
109 def construct(options
, system
, ruby_system
):
110 if (buildEnv
['PROTOCOL'] != 'GPU_VIPER' or
111 buildEnv
['PROTOCOL'] != 'GPU_VIPER_Region' or
112 buildEnv
['PROTOCOL'] != 'GPU_VIPER_Baseline'):
113 panic("This script requires VIPER based protocols \
117 cpuCluster
= Cluster(name
="CPU Cluster", extBW
= 8, intBW
=8) # 16 GB/s
118 for i
in range((options
.num_cpus
+ 1) // 2):
121 cp_cntrl
.create(options
, ruby_system
, system
)
123 # Connect the CP controllers to the ruby network
124 cp_cntrl
.requestFromCore
= ruby_system
.network
.slave
125 cp_cntrl
.responseFromCore
= ruby_system
.network
.slave
126 cp_cntrl
.unblockFromCore
= ruby_system
.network
.slave
127 cp_cntrl
.probeToCore
= ruby_system
.network
.master
128 cp_cntrl
.responseToCore
= ruby_system
.network
.master
130 exec("system.cp_cntrl%d = cp_cntrl" % i
)
132 # Add controllers and sequencers to the appropriate lists
134 cpu_sequencers
.extend([cp_cntrl
.sequencer
, cp_cntrl
.sequencer1
])
135 cpuCluster
.add(cp_cntrl
)
136 return cpu_sequencers
, cpuCluster