configs/ruby/AMD_Base_Constructor.py

   1 # Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
   2 # All rights reserved.
   3 #
   4 # For use for simulation and test purposes only
   5 #
   6 # Redistribution and use in source and binary forms, with or without
   7 # modification, are permitted provided that the following conditions are met:
   8 #
   9 # 1. Redistributions of source code must retain the above copyright notice,
  10 # this list of conditions and the following disclaimer.
  11 #
  12 # 2. Redistributions in binary form must reproduce the above copyright notice,
  13 # this list of conditions and the following disclaimer in the documentation
  14 # and/or other materials provided with the distribution.
  15 #
  16 # 3. Neither the name of the copyright holder nor the names of its
  17 # contributors may be used to endorse or promote products derived from this
  18 # software without specific prior written permission.
  19 #
  20 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  24 # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 # POSSIBILITY OF SUCH DAMAGE.
  31
  32 import math
  33 import m5
  34 from m5.objects import *
  35 from m5.defines import buildEnv
  36 from m5.util import addToPath, convert
  37 from .CntrlBase import *
  38
  39 addToPath('../')
  40
  41 from topologies.Cluster import Cluster
  42
  43 #
  44 # Note: the L1 Cache latency is only used by the sequencer on fast path hits
  45 #
  46 class L1Cache(RubyCache):
  47     latency = 1
  48     resourceStalls = False
  49     def create(self, size, assoc, options):
  50         self.size = MemorySize(size)
  51         self.assoc = assoc
  52         self.replacement_policy = TreePLRURP()
  53
  54 #
  55 # Note: the L2 Cache latency is not currently used
  56 #
  57 class L2Cache(RubyCache):
  58     latency = 10
  59     resourceStalls = False
  60     def create(self, size, assoc, options):
  61         self.size = MemorySize(size)
  62         self.assoc = assoc
  63         self.replacement_policy = TreePLRURP()
  64 class CPCntrl(AMD_Base_Controller, CntrlBase):
  65
  66     def create(self, options, ruby_system, system):
  67         self.version = self.versionCount()
  68         self.cntrl_id = self.cntrlCount()
  69
  70         self.L1Icache = L1Cache()
  71         self.L1Icache.create(options.l1i_size, options.l1i_assoc, options)
  72         self.L1D0cache = L1Cache()
  73         self.L1D0cache.create(options.l1d_size, options.l1d_assoc, options)
  74         self.L1D1cache = L1Cache()
  75         self.L1D1cache.create(options.l1d_size, options.l1d_assoc, options)
  76         self.L2cache = L2Cache()
  77         self.L2cache.create(options.l2_size, options.l2_assoc, options)
  78
  79         self.sequencer = RubySequencer()
  80         self.sequencer.version = self.seqCount()
  81         self.sequencer.icache = self.L1Icache
  82         self.sequencer.dcache = self.L1D0cache
  83         self.sequencer.ruby_system = ruby_system
  84         self.sequencer.coreid = 0
  85         self.sequencer.is_cpu_sequencer = True
  86
  87         self.sequencer1 = RubySequencer()
  88         self.sequencer1.version = self.seqCount()
  89         self.sequencer1.icache = self.L1Icache
  90         self.sequencer1.dcache = self.L1D1cache
  91         self.sequencer1.ruby_system = ruby_system
  92         self.sequencer1.coreid = 1
  93         self.sequencer1.is_cpu_sequencer = True
  94
  95         self.issue_latency = options.cpu_to_dir_latency
  96         self.send_evictions = send_evicts(options)
  97
  98         self.ruby_system = ruby_system
  99
 100         if options.recycle_latency:
 101             self.recycle_latency = options.recycle_latency
 102
 103 def define_options(parser):
 104     parser.add_option("--cpu-to-dir-latency", type="int", default=15)
 105
 106 def construct(options, system, ruby_system):
 107     if (buildEnv['PROTOCOL'] != 'GPU_VIPER' or
 108         buildEnv['PROTOCOL'] != 'GPU_VIPER_Region' or
 109         buildEnv['PROTOCOL'] != 'GPU_VIPER_Baseline'):
 110         panic("This script requires VIPER based protocols \
 111         to be built.")
 112     cpu_sequencers = []
 113     cpuCluster = None
 114     cpuCluster = Cluster(name="CPU Cluster", extBW = 8, intBW=8) # 16 GB/s
 115     for i in range((options.num_cpus + 1) // 2):
 116
 117         cp_cntrl = CPCntrl()
 118         cp_cntrl.create(options, ruby_system, system)
 119
 120         # Connect the CP controllers to the ruby network
 121         cp_cntrl.requestFromCore = ruby_system.network.slave
 122         cp_cntrl.responseFromCore = ruby_system.network.slave
 123         cp_cntrl.unblockFromCore = ruby_system.network.slave
 124         cp_cntrl.probeToCore = ruby_system.network.master
 125         cp_cntrl.responseToCore = ruby_system.network.master
 126
 127         exec("system.cp_cntrl%d = cp_cntrl" % i)
 128         #
 129         # Add controllers and sequencers to the appropriate lists
 130         #
 131         cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1])
 132         cpuCluster.add(cp_cntrl)
 133     return cpu_sequencers, cpuCluster