configs, mem-ruby: fix issues with style in AMD license
[gem5.git] / configs / ruby / GPU_VIPER.py
1 # Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
2 # All rights reserved.
3 #
4 # For use for simulation and test purposes only
5 #
6 # Redistribution and use in source and binary forms, with or without
7 # modification, are permitted provided that the following conditions are met:
8 #
9 # 1. Redistributions of source code must retain the above copyright notice,
10 # this list of conditions and the following disclaimer.
11 #
12 # 2. Redistributions in binary form must reproduce the above copyright notice,
13 # this list of conditions and the following disclaimer in the documentation
14 # and/or other materials provided with the distribution.
15 #
16 # 3. Neither the name of the copyright holder nor the names of its
17 # contributors may be used to endorse or promote products derived from this
18 # software without specific prior written permission.
19 #
20 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
24 # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 # POSSIBILITY OF SUCH DAMAGE.
31 #
32 # Authors: Lisa Hsu
33
34 import math
35 import m5
36 from m5.objects import *
37 from m5.defines import buildEnv
38 from Ruby import create_topology
39 from Ruby import send_evicts
40
41 from topologies.Cluster import Cluster
42 from topologies.Crossbar import Crossbar
43
44 class CntrlBase:
45 _seqs = 0
46 @classmethod
47 def seqCount(cls):
48 # Use SeqCount not class since we need global count
49 CntrlBase._seqs += 1
50 return CntrlBase._seqs - 1
51
52 _cntrls = 0
53 @classmethod
54 def cntrlCount(cls):
55 # Use CntlCount not class since we need global count
56 CntrlBase._cntrls += 1
57 return CntrlBase._cntrls - 1
58
59 _version = 0
60 @classmethod
61 def versionCount(cls):
62 cls._version += 1 # Use count for this particular type
63 return cls._version - 1
64
65 class L1Cache(RubyCache):
66 resourceStalls = False
67 dataArrayBanks = 2
68 tagArrayBanks = 2
69 dataAccessLatency = 1
70 tagAccessLatency = 1
71 def create(self, size, assoc, options):
72 self.size = MemorySize(size)
73 self.assoc = assoc
74 self.replacement_policy = PseudoLRUReplacementPolicy()
75
76 class L2Cache(RubyCache):
77 resourceStalls = False
78 assoc = 16
79 dataArrayBanks = 16
80 tagArrayBanks = 16
81 def create(self, size, assoc, options):
82 self.size = MemorySize(size)
83 self.assoc = assoc
84 self.replacement_policy = PseudoLRUReplacementPolicy()
85
86 class CPCntrl(CorePair_Controller, CntrlBase):
87
88 def create(self, options, ruby_system, system):
89 self.version = self.versionCount()
90
91 self.L1Icache = L1Cache()
92 self.L1Icache.create(options.l1i_size, options.l1i_assoc, options)
93 self.L1D0cache = L1Cache()
94 self.L1D0cache.create(options.l1d_size, options.l1d_assoc, options)
95 self.L1D1cache = L1Cache()
96 self.L1D1cache.create(options.l1d_size, options.l1d_assoc, options)
97 self.L2cache = L2Cache()
98 self.L2cache.create(options.l2_size, options.l2_assoc, options)
99
100 self.sequencer = RubySequencer()
101 self.sequencer.version = self.seqCount()
102 self.sequencer.icache = self.L1Icache
103 self.sequencer.dcache = self.L1D0cache
104 self.sequencer.ruby_system = ruby_system
105 self.sequencer.coreid = 0
106 self.sequencer.is_cpu_sequencer = True
107
108 self.sequencer1 = RubySequencer()
109 self.sequencer1.version = self.seqCount()
110 self.sequencer1.icache = self.L1Icache
111 self.sequencer1.dcache = self.L1D1cache
112 self.sequencer1.ruby_system = ruby_system
113 self.sequencer1.coreid = 1
114 self.sequencer1.is_cpu_sequencer = True
115
116 self.issue_latency = options.cpu_to_dir_latency
117 self.send_evictions = send_evicts(options)
118
119 self.ruby_system = ruby_system
120
121 if options.recycle_latency:
122 self.recycle_latency = options.recycle_latency
123
124 class TCPCache(RubyCache):
125 size = "16kB"
126 assoc = 16
127 dataArrayBanks = 16 #number of data banks
128 tagArrayBanks = 16 #number of tag banks
129 dataAccessLatency = 4
130 tagAccessLatency = 1
131 def create(self, options):
132 self.size = MemorySize(options.tcp_size)
133 self.assoc = options.tcp_assoc
134 self.resourceStalls = options.no_tcc_resource_stalls
135 self.replacement_policy = PseudoLRUReplacementPolicy()
136
137 class TCPCntrl(TCP_Controller, CntrlBase):
138
139 def create(self, options, ruby_system, system):
140 self.version = self.versionCount()
141
142 self.L1cache = TCPCache(tagAccessLatency = options.TCP_latency,
143 dataAccessLatency = options.TCP_latency)
144 self.L1cache.resourceStalls = options.no_resource_stalls
145 self.L1cache.create(options)
146 self.issue_latency = 1
147
148 self.coalescer = VIPERCoalescer()
149 self.coalescer.version = self.seqCount()
150 self.coalescer.icache = self.L1cache
151 self.coalescer.dcache = self.L1cache
152 self.coalescer.ruby_system = ruby_system
153 self.coalescer.support_inst_reqs = False
154 self.coalescer.is_cpu_sequencer = False
155
156 self.sequencer = RubySequencer()
157 self.sequencer.version = self.seqCount()
158 self.sequencer.icache = self.L1cache
159 self.sequencer.dcache = self.L1cache
160 self.sequencer.ruby_system = ruby_system
161 self.sequencer.is_cpu_sequencer = True
162
163 self.use_seq_not_coal = False
164
165 self.ruby_system = ruby_system
166
167 if options.recycle_latency:
168 self.recycle_latency = options.recycle_latency
169
170 def createCP(self, options, ruby_system, system):
171 self.version = self.versionCount()
172
173 self.L1cache = TCPCache(tagAccessLatency = options.TCP_latency,
174 dataAccessLatency = options.TCP_latency)
175 self.L1cache.resourceStalls = options.no_resource_stalls
176 self.L1cache.create(options)
177 self.issue_latency = 1
178
179 self.coalescer = VIPERCoalescer()
180 self.coalescer.version = self.seqCount()
181 self.coalescer.icache = self.L1cache
182 self.coalescer.dcache = self.L1cache
183 self.coalescer.ruby_system = ruby_system
184 self.coalescer.support_inst_reqs = False
185 self.coalescer.is_cpu_sequencer = False
186
187 self.sequencer = RubySequencer()
188 self.sequencer.version = self.seqCount()
189 self.sequencer.icache = self.L1cache
190 self.sequencer.dcache = self.L1cache
191 self.sequencer.ruby_system = ruby_system
192 self.sequencer.is_cpu_sequencer = True
193
194 self.use_seq_not_coal = True
195
196 self.ruby_system = ruby_system
197
198 if options.recycle_latency:
199 self.recycle_latency = options.recycle_latency
200
201 class SQCCache(RubyCache):
202 dataArrayBanks = 8
203 tagArrayBanks = 8
204 dataAccessLatency = 1
205 tagAccessLatency = 1
206
207 def create(self, options):
208 self.size = MemorySize(options.sqc_size)
209 self.assoc = options.sqc_assoc
210 self.replacement_policy = PseudoLRUReplacementPolicy()
211
212 class SQCCntrl(SQC_Controller, CntrlBase):
213
214 def create(self, options, ruby_system, system):
215 self.version = self.versionCount()
216
217 self.L1cache = SQCCache()
218 self.L1cache.create(options)
219 self.L1cache.resourceStalls = options.no_resource_stalls
220
221 self.sequencer = RubySequencer()
222
223 self.sequencer.version = self.seqCount()
224 self.sequencer.icache = self.L1cache
225 self.sequencer.dcache = self.L1cache
226 self.sequencer.ruby_system = ruby_system
227 self.sequencer.support_data_reqs = False
228 self.sequencer.is_cpu_sequencer = False
229
230 self.ruby_system = ruby_system
231
232 if options.recycle_latency:
233 self.recycle_latency = options.recycle_latency
234
235 class TCC(RubyCache):
236 size = MemorySize("256kB")
237 assoc = 16
238 dataAccessLatency = 8
239 tagAccessLatency = 2
240 resourceStalls = True
241 def create(self, options):
242 self.assoc = options.tcc_assoc
243 if hasattr(options, 'bw_scalor') and options.bw_scalor > 0:
244 s = options.num_compute_units
245 tcc_size = s * 128
246 tcc_size = str(tcc_size)+'kB'
247 self.size = MemorySize(tcc_size)
248 self.dataArrayBanks = 64
249 self.tagArrayBanks = 64
250 else:
251 self.size = MemorySize(options.tcc_size)
252 self.dataArrayBanks = 256 / options.num_tccs #number of data banks
253 self.tagArrayBanks = 256 / options.num_tccs #number of tag banks
254 self.size.value = self.size.value / options.num_tccs
255 if ((self.size.value / long(self.assoc)) < 128):
256 self.size.value = long(128 * self.assoc)
257 self.start_index_bit = math.log(options.cacheline_size, 2) + \
258 math.log(options.num_tccs, 2)
259 self.replacement_policy = PseudoLRUReplacementPolicy()
260
261
262 class TCCCntrl(TCC_Controller, CntrlBase):
263 def create(self, options, ruby_system, system):
264 self.version = self.versionCount()
265 self.L2cache = TCC()
266 self.L2cache.create(options)
267 self.L2cache.resourceStalls = options.no_tcc_resource_stalls
268
269 self.ruby_system = ruby_system
270
271 if options.recycle_latency:
272 self.recycle_latency = options.recycle_latency
273
274 class L3Cache(RubyCache):
275 dataArrayBanks = 16
276 tagArrayBanks = 16
277
278 def create(self, options, ruby_system, system):
279 self.size = MemorySize(options.l3_size)
280 self.size.value /= options.num_dirs
281 self.assoc = options.l3_assoc
282 self.dataArrayBanks /= options.num_dirs
283 self.tagArrayBanks /= options.num_dirs
284 self.dataArrayBanks /= options.num_dirs
285 self.tagArrayBanks /= options.num_dirs
286 self.dataAccessLatency = options.l3_data_latency
287 self.tagAccessLatency = options.l3_tag_latency
288 self.resourceStalls = False
289 self.replacement_policy = PseudoLRUReplacementPolicy()
290
291 class L3Cntrl(L3Cache_Controller, CntrlBase):
292 def create(self, options, ruby_system, system):
293 self.version = self.versionCount()
294 self.L3cache = L3Cache()
295 self.L3cache.create(options, ruby_system, system)
296
297 self.l3_response_latency = max(self.L3cache.dataAccessLatency, self.L3cache.tagAccessLatency)
298 self.ruby_system = ruby_system
299
300 if options.recycle_latency:
301 self.recycle_latency = options.recycle_latency
302
303 def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir,
304 req_to_l3, probe_to_l3, resp_to_l3):
305 self.reqToDir = req_to_dir
306 self.respToDir = resp_to_dir
307 self.l3UnblockToDir = l3_unblock_to_dir
308 self.reqToL3 = req_to_l3
309 self.probeToL3 = probe_to_l3
310 self.respToL3 = resp_to_l3
311
312 class DirMem(RubyDirectoryMemory, CntrlBase):
313 def create(self, options, ruby_system, system):
314 self.version = self.versionCount()
315
316 phys_mem_size = AddrRange(options.mem_size).size()
317 mem_module_size = phys_mem_size / options.num_dirs
318 dir_size = MemorySize('0B')
319 dir_size.value = mem_module_size
320 self.size = dir_size
321
322 class DirCntrl(Directory_Controller, CntrlBase):
323 def create(self, options, ruby_system, system):
324 self.version = self.versionCount()
325
326 self.response_latency = 30
327
328 self.directory = DirMem()
329 self.directory.create(options, ruby_system, system)
330
331 self.L3CacheMemory = L3Cache()
332 self.L3CacheMemory.create(options, ruby_system, system)
333
334 self.l3_hit_latency = max(self.L3CacheMemory.dataAccessLatency,
335 self.L3CacheMemory.tagAccessLatency)
336
337 self.number_of_TBEs = options.num_tbes
338
339 self.ruby_system = ruby_system
340
341 if options.recycle_latency:
342 self.recycle_latency = options.recycle_latency
343
344 def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir,
345 req_to_l3, probe_to_l3, resp_to_l3):
346 self.reqToDir = req_to_dir
347 self.respToDir = resp_to_dir
348 self.l3UnblockToDir = l3_unblock_to_dir
349 self.reqToL3 = req_to_l3
350 self.probeToL3 = probe_to_l3
351 self.respToL3 = resp_to_l3
352
353 def define_options(parser):
354 parser.add_option("--num-subcaches", type = "int", default = 4)
355 parser.add_option("--l3-data-latency", type = "int", default = 20)
356 parser.add_option("--l3-tag-latency", type = "int", default = 15)
357 parser.add_option("--cpu-to-dir-latency", type = "int", default = 120)
358 parser.add_option("--gpu-to-dir-latency", type = "int", default = 120)
359 parser.add_option("--no-resource-stalls", action = "store_false",
360 default = True)
361 parser.add_option("--no-tcc-resource-stalls", action = "store_false",
362 default = True)
363 parser.add_option("--use-L3-on-WT", action = "store_true", default = False)
364 parser.add_option("--num-tbes", type = "int", default = 256)
365 parser.add_option("--l2-latency", type = "int", default = 50) # load to use
366 parser.add_option("--num-tccs", type = "int", default = 1,
367 help = "number of TCC banks in the GPU")
368 parser.add_option("--sqc-size", type = 'string', default = '32kB',
369 help = "SQC cache size")
370 parser.add_option("--sqc-assoc", type = 'int', default = 8,
371 help = "SQC cache assoc")
372 parser.add_option("--WB_L1", action = "store_true", default = False,
373 help = "writeback L1")
374 parser.add_option("--WB_L2", action = "store_true", default = False,
375 help = "writeback L2")
376 parser.add_option("--TCP_latency", type = "int", default = 4,
377 help = "TCP latency")
378 parser.add_option("--TCC_latency", type = "int", default = 16,
379 help = "TCC latency")
380 parser.add_option("--tcc-size", type = 'string', default = '256kB',
381 help = "agregate tcc size")
382 parser.add_option("--tcc-assoc", type = 'int', default = 16,
383 help = "tcc assoc")
384 parser.add_option("--tcp-size", type = 'string', default = '16kB',
385 help = "tcp size")
386 parser.add_option("--tcp-assoc", type = 'int', default = 16,
387 help = "tcp assoc")
388 parser.add_option("--noL1", action = "store_true", default = False,
389 help = "bypassL1")
390
391 def create_system(options, full_system, system, dma_devices, bootmem,
392 ruby_system):
393 if buildEnv['PROTOCOL'] != 'GPU_VIPER':
394 panic("This script requires the GPU_VIPER protocol to be built.")
395
396 cpu_sequencers = []
397
398 #
399 # The ruby network creation expects the list of nodes in the system to be
400 # consistent with the NetDest list. Therefore the l1 controller nodes
401 # must be listed before the directory nodes and directory nodes before
402 # dma nodes, etc.
403 #
404 cp_cntrl_nodes = []
405 tcp_cntrl_nodes = []
406 sqc_cntrl_nodes = []
407 tcc_cntrl_nodes = []
408 dir_cntrl_nodes = []
409 l3_cntrl_nodes = []
410
411 #
412 # Must create the individual controllers before the network to ensure the
413 # controller constructors are called before the network constructor
414 #
415
416 # For an odd number of CPUs, still create the right number of controllers
417 TCC_bits = int(math.log(options.num_tccs, 2))
418
419 # This is the base crossbar that connects the L3s, Dirs, and cpu/gpu
420 # Clusters
421 crossbar_bw = None
422 mainCluster = None
423 if hasattr(options, 'bw_scalor') and options.bw_scalor > 0:
424 #Assuming a 2GHz clock
425 crossbar_bw = 16 * options.num_compute_units * options.bw_scalor
426 mainCluster = Cluster(intBW=crossbar_bw)
427 else:
428 mainCluster = Cluster(intBW=8) # 16 GB/s
429 for i in xrange(options.num_dirs):
430
431 dir_cntrl = DirCntrl(noTCCdir = True, TCC_select_num_bits = TCC_bits)
432 dir_cntrl.create(options, ruby_system, system)
433 dir_cntrl.number_of_TBEs = options.num_tbes
434 dir_cntrl.useL3OnWT = options.use_L3_on_WT
435 # the number_of_TBEs is inclusive of TBEs below
436
437 # Connect the Directory controller to the ruby network
438 dir_cntrl.requestFromCores = MessageBuffer(ordered = True)
439 dir_cntrl.requestFromCores.slave = ruby_system.network.master
440
441 dir_cntrl.responseFromCores = MessageBuffer()
442 dir_cntrl.responseFromCores.slave = ruby_system.network.master
443
444 dir_cntrl.unblockFromCores = MessageBuffer()
445 dir_cntrl.unblockFromCores.slave = ruby_system.network.master
446
447 dir_cntrl.probeToCore = MessageBuffer()
448 dir_cntrl.probeToCore.master = ruby_system.network.slave
449
450 dir_cntrl.responseToCore = MessageBuffer()
451 dir_cntrl.responseToCore.master = ruby_system.network.slave
452
453 dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
454 dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True)
455 dir_cntrl.responseFromMemory = MessageBuffer()
456
457 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
458 dir_cntrl_nodes.append(dir_cntrl)
459
460 mainCluster.add(dir_cntrl)
461
462 cpuCluster = None
463 if hasattr(options, 'bw_scalor') and options.bw_scalor > 0:
464 cpuCluster = Cluster(extBW = crossbar_bw, intBW = crossbar_bw)
465 else:
466 cpuCluster = Cluster(extBW = 8, intBW = 8) # 16 GB/s
467 for i in xrange((options.num_cpus + 1) / 2):
468
469 cp_cntrl = CPCntrl()
470 cp_cntrl.create(options, ruby_system, system)
471
472 exec("ruby_system.cp_cntrl%d = cp_cntrl" % i)
473 #
474 # Add controllers and sequencers to the appropriate lists
475 #
476 cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1])
477
478 # Connect the CP controllers and the network
479 cp_cntrl.requestFromCore = MessageBuffer()
480 cp_cntrl.requestFromCore.master = ruby_system.network.slave
481
482 cp_cntrl.responseFromCore = MessageBuffer()
483 cp_cntrl.responseFromCore.master = ruby_system.network.slave
484
485 cp_cntrl.unblockFromCore = MessageBuffer()
486 cp_cntrl.unblockFromCore.master = ruby_system.network.slave
487
488 cp_cntrl.probeToCore = MessageBuffer()
489 cp_cntrl.probeToCore.slave = ruby_system.network.master
490
491 cp_cntrl.responseToCore = MessageBuffer()
492 cp_cntrl.responseToCore.slave = ruby_system.network.master
493
494 cp_cntrl.mandatoryQueue = MessageBuffer()
495 cp_cntrl.triggerQueue = MessageBuffer(ordered = True)
496
497 cpuCluster.add(cp_cntrl)
498
499 gpuCluster = None
500 if hasattr(options, 'bw_scalor') and options.bw_scalor > 0:
501 gpuCluster = Cluster(extBW = crossbar_bw, intBW = crossbar_bw)
502 else:
503 gpuCluster = Cluster(extBW = 8, intBW = 8) # 16 GB/s
504 for i in xrange(options.num_compute_units):
505
506 tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits,
507 issue_latency = 1,
508 number_of_TBEs = 2560)
509 # TBEs set to max outstanding requests
510 tcp_cntrl.create(options, ruby_system, system)
511 tcp_cntrl.WB = options.WB_L1
512 tcp_cntrl.disableL1 = options.noL1
513 tcp_cntrl.L1cache.tagAccessLatency = options.TCP_latency
514 tcp_cntrl.L1cache.dataAccessLatency = options.TCP_latency
515
516 exec("ruby_system.tcp_cntrl%d = tcp_cntrl" % i)
517 #
518 # Add controllers and sequencers to the appropriate lists
519 #
520 cpu_sequencers.append(tcp_cntrl.coalescer)
521 tcp_cntrl_nodes.append(tcp_cntrl)
522
523 # Connect the TCP controller to the ruby network
524 tcp_cntrl.requestFromTCP = MessageBuffer(ordered = True)
525 tcp_cntrl.requestFromTCP.master = ruby_system.network.slave
526
527 tcp_cntrl.responseFromTCP = MessageBuffer(ordered = True)
528 tcp_cntrl.responseFromTCP.master = ruby_system.network.slave
529
530 tcp_cntrl.unblockFromCore = MessageBuffer()
531 tcp_cntrl.unblockFromCore.master = ruby_system.network.slave
532
533 tcp_cntrl.probeToTCP = MessageBuffer(ordered = True)
534 tcp_cntrl.probeToTCP.slave = ruby_system.network.master
535
536 tcp_cntrl.responseToTCP = MessageBuffer(ordered = True)
537 tcp_cntrl.responseToTCP.slave = ruby_system.network.master
538
539 tcp_cntrl.mandatoryQueue = MessageBuffer()
540
541 gpuCluster.add(tcp_cntrl)
542
543 for i in xrange(options.num_sqc):
544
545 sqc_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits)
546 sqc_cntrl.create(options, ruby_system, system)
547
548 exec("ruby_system.sqc_cntrl%d = sqc_cntrl" % i)
549 #
550 # Add controllers and sequencers to the appropriate lists
551 #
552 cpu_sequencers.append(sqc_cntrl.sequencer)
553
554 # Connect the SQC controller to the ruby network
555 sqc_cntrl.requestFromSQC = MessageBuffer(ordered = True)
556 sqc_cntrl.requestFromSQC.master = ruby_system.network.slave
557
558 sqc_cntrl.probeToSQC = MessageBuffer(ordered = True)
559 sqc_cntrl.probeToSQC.slave = ruby_system.network.master
560
561 sqc_cntrl.responseToSQC = MessageBuffer(ordered = True)
562 sqc_cntrl.responseToSQC.slave = ruby_system.network.master
563
564 sqc_cntrl.mandatoryQueue = MessageBuffer()
565
566 # SQC also in GPU cluster
567 gpuCluster.add(sqc_cntrl)
568
569 for i in xrange(options.num_cp):
570
571 tcp_ID = options.num_compute_units + i
572 sqc_ID = options.num_sqc + i
573
574 tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits,
575 issue_latency = 1,
576 number_of_TBEs = 2560)
577 # TBEs set to max outstanding requests
578 tcp_cntrl.createCP(options, ruby_system, system)
579 tcp_cntrl.WB = options.WB_L1
580 tcp_cntrl.disableL1 = options.noL1
581 tcp_cntrl.L1cache.tagAccessLatency = options.TCP_latency
582 tcp_cntrl.L1cache.dataAccessLatency = options.TCP_latency
583
584 exec("ruby_system.tcp_cntrl%d = tcp_cntrl" % tcp_ID)
585 #
586 # Add controllers and sequencers to the appropriate lists
587 #
588 cpu_sequencers.append(tcp_cntrl.sequencer)
589 tcp_cntrl_nodes.append(tcp_cntrl)
590
591 # Connect the CP (TCP) controllers to the ruby network
592 tcp_cntrl.requestFromTCP = MessageBuffer(ordered = True)
593 tcp_cntrl.requestFromTCP.master = ruby_system.network.slave
594
595 tcp_cntrl.responseFromTCP = MessageBuffer(ordered = True)
596 tcp_cntrl.responseFromTCP.master = ruby_system.network.slave
597
598 tcp_cntrl.unblockFromCore = MessageBuffer(ordered = True)
599 tcp_cntrl.unblockFromCore.master = ruby_system.network.slave
600
601 tcp_cntrl.probeToTCP = MessageBuffer(ordered = True)
602 tcp_cntrl.probeToTCP.slave = ruby_system.network.master
603
604 tcp_cntrl.responseToTCP = MessageBuffer(ordered = True)
605 tcp_cntrl.responseToTCP.slave = ruby_system.network.master
606
607 tcp_cntrl.mandatoryQueue = MessageBuffer()
608
609 gpuCluster.add(tcp_cntrl)
610
611 sqc_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits)
612 sqc_cntrl.create(options, ruby_system, system)
613
614 exec("ruby_system.sqc_cntrl%d = sqc_cntrl" % sqc_ID)
615 #
616 # Add controllers and sequencers to the appropriate lists
617 #
618 cpu_sequencers.append(sqc_cntrl.sequencer)
619
620 # SQC also in GPU cluster
621 gpuCluster.add(sqc_cntrl)
622
623 for i in xrange(options.num_tccs):
624
625 tcc_cntrl = TCCCntrl(l2_response_latency = options.TCC_latency)
626 tcc_cntrl.create(options, ruby_system, system)
627 tcc_cntrl.l2_request_latency = options.gpu_to_dir_latency
628 tcc_cntrl.l2_response_latency = options.TCC_latency
629 tcc_cntrl_nodes.append(tcc_cntrl)
630 tcc_cntrl.WB = options.WB_L2
631 tcc_cntrl.number_of_TBEs = 2560 * options.num_compute_units
632 # the number_of_TBEs is inclusive of TBEs below
633
634 # Connect the TCC controllers to the ruby network
635 tcc_cntrl.requestFromTCP = MessageBuffer(ordered = True)
636 tcc_cntrl.requestFromTCP.slave = ruby_system.network.master
637
638 tcc_cntrl.responseToCore = MessageBuffer(ordered = True)
639 tcc_cntrl.responseToCore.master = ruby_system.network.slave
640
641 tcc_cntrl.probeFromNB = MessageBuffer()
642 tcc_cntrl.probeFromNB.slave = ruby_system.network.master
643
644 tcc_cntrl.responseFromNB = MessageBuffer()
645 tcc_cntrl.responseFromNB.slave = ruby_system.network.master
646
647 tcc_cntrl.requestToNB = MessageBuffer(ordered = True)
648 tcc_cntrl.requestToNB.master = ruby_system.network.slave
649
650 tcc_cntrl.responseToNB = MessageBuffer()
651 tcc_cntrl.responseToNB.master = ruby_system.network.slave
652
653 tcc_cntrl.unblockToNB = MessageBuffer()
654 tcc_cntrl.unblockToNB.master = ruby_system.network.slave
655
656 tcc_cntrl.triggerQueue = MessageBuffer(ordered = True)
657
658 exec("ruby_system.tcc_cntrl%d = tcc_cntrl" % i)
659
660 # connect all of the wire buffers between L3 and dirs up
661 # TCC cntrls added to the GPU cluster
662 gpuCluster.add(tcc_cntrl)
663
664 # Assuming no DMA devices
665 assert(len(dma_devices) == 0)
666
667 # Add cpu/gpu clusters to main cluster
668 mainCluster.add(cpuCluster)
669 mainCluster.add(gpuCluster)
670
671 ruby_system.network.number_of_virtual_networks = 10
672
673 return (cpu_sequencers, dir_cntrl_nodes, mainCluster)