1 # Copyright (c) 2015 Advanced Micro Devices, Inc.
4 # For use for simulation and test purposes only
6 # Redistribution and use in source and binary forms, with or without
7 # modification, are permitted provided that the following conditions are met:
9 # 1. Redistributions of source code must retain the above copyright notice,
10 # this list of conditions and the following disclaimer.
12 # 2. Redistributions in binary form must reproduce the above copyright notice,
13 # this list of conditions and the following disclaimer in the documentation
14 # and/or other materials provided with the distribution.
16 # 3. Neither the name of the copyright holder nor the names of its
17 # contributors may be used to endorse or promote products derived from this
18 # software without specific prior written permission.
20 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
24 # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 # POSSIBILITY OF SUCH DAMAGE.
35 from m5
.objects
import *
36 from m5
.defines
import buildEnv
37 from m5
.util
import addToPath
38 from .Ruby
import create_topology
39 from .Ruby
import send_evicts
43 from topologies
.Cluster
import Cluster
44 from topologies
.Crossbar
import Crossbar
53 # Use SeqCount not class since we need global count
55 return CntrlBase
._seqs
- 1
60 # Use CntlCount not class since we need global count
61 CntrlBase
._cntrls
+= 1
62 return CntrlBase
._cntrls
- 1
66 def versionCount(cls
):
67 cls
._version
+= 1 # Use count for this particular type
68 return cls
._version
- 1
70 class L1Cache(RubyCache
):
71 resourceStalls
= False
76 def create(self
, size
, assoc
, options
):
77 self
.size
= MemorySize(size
)
79 self
.replacement_policy
= TreePLRURP()
81 class L2Cache(RubyCache
):
82 resourceStalls
= False
86 def create(self
, size
, assoc
, options
):
87 self
.size
= MemorySize(size
)
89 self
.replacement_policy
= TreePLRURP()
91 class CPCntrl(CorePair_Controller
, CntrlBase
):
93 def create(self
, options
, ruby_system
, system
):
94 self
.version
= self
.versionCount()
96 self
.L1Icache
= L1Cache()
97 self
.L1Icache
.create(options
.l1i_size
, options
.l1i_assoc
, options
)
98 self
.L1D0cache
= L1Cache()
99 self
.L1D0cache
.create(options
.l1d_size
, options
.l1d_assoc
, options
)
100 self
.L1D1cache
= L1Cache()
101 self
.L1D1cache
.create(options
.l1d_size
, options
.l1d_assoc
, options
)
102 self
.L2cache
= L2Cache()
103 self
.L2cache
.create(options
.l2_size
, options
.l2_assoc
, options
)
105 self
.sequencer
= RubySequencer()
106 self
.sequencer
.version
= self
.seqCount()
107 self
.sequencer
.dcache
= self
.L1D0cache
108 self
.sequencer
.ruby_system
= ruby_system
109 self
.sequencer
.coreid
= 0
110 self
.sequencer
.is_cpu_sequencer
= True
112 self
.sequencer1
= RubySequencer()
113 self
.sequencer1
.version
= self
.seqCount()
114 self
.sequencer1
.dcache
= self
.L1D1cache
115 self
.sequencer1
.ruby_system
= ruby_system
116 self
.sequencer1
.coreid
= 1
117 self
.sequencer1
.is_cpu_sequencer
= True
119 self
.issue_latency
= options
.cpu_to_dir_latency
120 self
.send_evictions
= send_evicts(options
)
122 self
.ruby_system
= ruby_system
124 if options
.recycle_latency
:
125 self
.recycle_latency
= options
.recycle_latency
127 class TCPCache(RubyCache
):
132 dataAccessLatency
= 4
134 def create(self
, options
):
135 self
.size
= MemorySize(options
.tcp_size
)
136 self
.dataArrayBanks
= 16
137 self
.tagArrayBanks
= 16
138 self
.dataAccessLatency
= 4
139 self
.tagAccessLatency
= 1
140 self
.resourceStalls
= options
.no_tcc_resource_stalls
141 self
.replacement_policy
= TreePLRURP()
143 class TCPCntrl(TCP_Controller
, CntrlBase
):
145 def create(self
, options
, ruby_system
, system
):
146 self
.version
= self
.versionCount()
147 self
.L1cache
= TCPCache()
148 self
.L1cache
.create(options
)
149 self
.issue_latency
= 1
151 self
.coalescer
= VIPERCoalescer()
152 self
.coalescer
.version
= self
.seqCount()
153 self
.coalescer
.icache
= self
.L1cache
154 self
.coalescer
.dcache
= self
.L1cache
155 self
.coalescer
.ruby_system
= ruby_system
156 self
.coalescer
.support_inst_reqs
= False
157 self
.coalescer
.is_cpu_sequencer
= False
158 if options
.tcp_deadlock_threshold
:
159 self
.coalescer
.deadlock_threshold
= \
160 options
.tcp_deadlock_threshold
161 self
.coalescer
.max_coalesces_per_cycle
= \
162 options
.max_coalesces_per_cycle
164 self
.sequencer
= RubySequencer()
165 self
.sequencer
.version
= self
.seqCount()
166 self
.sequencer
.dcache
= self
.L1cache
167 self
.sequencer
.ruby_system
= ruby_system
168 self
.sequencer
.is_cpu_sequencer
= True
170 self
.use_seq_not_coal
= False
172 self
.ruby_system
= ruby_system
173 if options
.recycle_latency
:
174 self
.recycle_latency
= options
.recycle_latency
176 class SQCCache(RubyCache
):
179 dataAccessLatency
= 1
182 def create(self
, options
):
183 self
.size
= MemorySize(options
.sqc_size
)
184 self
.assoc
= options
.sqc_assoc
185 self
.replacement_policy
= TreePLRURP()
187 class SQCCntrl(SQC_Controller
, CntrlBase
):
189 def create(self
, options
, ruby_system
, system
):
190 self
.version
= self
.versionCount()
191 self
.L1cache
= SQCCache()
192 self
.L1cache
.create(options
)
193 self
.L1cache
.resourceStalls
= False
194 self
.sequencer
= RubySequencer()
195 self
.sequencer
.version
= self
.seqCount()
196 self
.sequencer
.dcache
= self
.L1cache
197 self
.sequencer
.ruby_system
= ruby_system
198 self
.sequencer
.support_data_reqs
= False
199 self
.sequencer
.is_cpu_sequencer
= False
200 if options
.sqc_deadlock_threshold
:
201 self
.sequencer
.deadlock_threshold
= \
202 options
.sqc_deadlock_threshold
204 self
.ruby_system
= ruby_system
205 if options
.recycle_latency
:
206 self
.recycle_latency
= options
.recycle_latency
208 class TCC(RubyCache
):
209 size
= MemorySize("256kB")
211 dataAccessLatency
= 8
213 resourceStalls
= True
214 def create(self
, options
):
215 self
.assoc
= options
.tcc_assoc
216 if hasattr(options
, 'bw_scalor') and options
.bw_scalor
> 0:
217 s
= options
.num_compute_units
219 tcc_size
= str(tcc_size
)+'kB'
220 self
.size
= MemorySize(tcc_size
)
221 self
.dataArrayBanks
= 64
222 self
.tagArrayBanks
= 64
224 self
.size
= MemorySize(options
.tcc_size
)
225 self
.dataArrayBanks
= 256 / options
.num_tccs
#number of data banks
226 self
.tagArrayBanks
= 256 / options
.num_tccs
#number of tag banks
227 self
.size
.value
= self
.size
.value
/ options
.num_tccs
228 if ((self
.size
.value
/ long(self
.assoc
)) < 128):
229 self
.size
.value
= long(128 * self
.assoc
)
230 self
.start_index_bit
= math
.log(options
.cacheline_size
, 2) + \
231 math
.log(options
.num_tccs
, 2)
232 self
.replacement_policy
= TreePLRURP()
234 class TCCCntrl(TCC_Controller
, CntrlBase
):
235 def create(self
, options
, ruby_system
, system
):
236 self
.version
= self
.versionCount()
238 self
.L2cache
.create(options
)
239 self
.ruby_system
= ruby_system
240 self
.L2cache
.resourceStalls
= options
.no_tcc_resource_stalls
242 if options
.recycle_latency
:
243 self
.recycle_latency
= options
.recycle_latency
245 class L3Cache(RubyCache
):
249 def create(self
, options
, ruby_system
, system
):
250 self
.size
= MemorySize(options
.l3_size
)
251 self
.size
.value
/= options
.num_dirs
252 self
.assoc
= options
.l3_assoc
253 self
.dataArrayBanks
/= options
.num_dirs
254 self
.tagArrayBanks
/= options
.num_dirs
255 self
.dataArrayBanks
/= options
.num_dirs
256 self
.tagArrayBanks
/= options
.num_dirs
257 self
.dataAccessLatency
= options
.l3_data_latency
258 self
.tagAccessLatency
= options
.l3_tag_latency
259 self
.resourceStalls
= False
260 self
.replacement_policy
= TreePLRURP()
262 class ProbeFilter(RubyCache
):
268 def create(self
, options
, ruby_system
, system
):
269 self
.block_size
= "%dB" % (64 * options
.blocks_per_region
)
270 self
.size
= options
.region_dir_entries
* \
271 self
.block_size
* options
.num_compute_units
273 self
.tagArrayBanks
= 8
274 self
.tagAccessLatency
= options
.dir_tag_latency
275 self
.dataAccessLatency
= 1
276 self
.resourceStalls
= options
.no_resource_stalls
277 self
.start_index_bit
= 6 + int(math
.log(options
.blocks_per_region
, 2))
278 self
.replacement_policy
= TreePLRURP()
280 class L3Cntrl(L3Cache_Controller
, CntrlBase
):
281 def create(self
, options
, ruby_system
, system
):
282 self
.version
= self
.versionCount()
283 self
.L3cache
= L3Cache()
284 self
.L3cache
.create(options
, ruby_system
, system
)
285 self
.l3_response_latency
= \
286 max(self
.L3cache
.dataAccessLatency
, self
.L3cache
.tagAccessLatency
)
287 self
.ruby_system
= ruby_system
288 if options
.recycle_latency
:
289 self
.recycle_latency
= options
.recycle_latency
291 def connectWireBuffers(self
, req_to_dir
, resp_to_dir
, l3_unblock_to_dir
,
292 req_to_l3
, probe_to_l3
, resp_to_l3
):
293 self
.reqToDir
= req_to_dir
294 self
.respToDir
= resp_to_dir
295 self
.l3UnblockToDir
= l3_unblock_to_dir
296 self
.reqToL3
= req_to_l3
297 self
.probeToL3
= probe_to_l3
298 self
.respToL3
= resp_to_l3
300 class DirCntrl(Directory_Controller
, CntrlBase
):
301 def create(self
, options
, dir_ranges
, ruby_system
, system
):
302 self
.version
= self
.versionCount()
303 self
.response_latency
= 30
304 self
.addr_ranges
= dir_ranges
305 self
.directory
= RubyDirectoryMemory()
306 self
.L3CacheMemory
= L3Cache()
307 self
.L3CacheMemory
.create(options
, ruby_system
, system
)
308 self
.ProbeFilterMemory
= ProbeFilter()
309 self
.ProbeFilterMemory
.create(options
, ruby_system
, system
)
310 self
.l3_hit_latency
= \
311 max(self
.L3CacheMemory
.dataAccessLatency
,
312 self
.L3CacheMemory
.tagAccessLatency
)
314 self
.ruby_system
= ruby_system
315 if options
.recycle_latency
:
316 self
.recycle_latency
= options
.recycle_latency
318 def connectWireBuffers(self
, req_to_dir
, resp_to_dir
, l3_unblock_to_dir
,
319 req_to_l3
, probe_to_l3
, resp_to_l3
):
320 self
.reqToDir
= req_to_dir
321 self
.respToDir
= resp_to_dir
322 self
.l3UnblockToDir
= l3_unblock_to_dir
323 self
.reqToL3
= req_to_l3
324 self
.probeToL3
= probe_to_l3
325 self
.respToL3
= resp_to_l3
327 def define_options(parser
):
328 parser
.add_option("--num-subcaches", type = "int", default
= 4)
329 parser
.add_option("--l3-data-latency", type = "int", default
= 20)
330 parser
.add_option("--l3-tag-latency", type = "int", default
= 15)
331 parser
.add_option("--cpu-to-dir-latency", type = "int", default
= 120)
332 parser
.add_option("--gpu-to-dir-latency", type = "int", default
= 120)
333 parser
.add_option("--no-resource-stalls", action
= "store_false",
335 parser
.add_option("--no-tcc-resource-stalls", action
= "store_false",
337 parser
.add_option("--num-tbes", type = "int", default
= 2560)
338 parser
.add_option("--l2-latency", type = "int", default
= 50) # load to use
339 parser
.add_option("--num-tccs", type = "int", default
= 1,
340 help = "number of TCC banks in the GPU")
341 parser
.add_option("--sqc-size", type = 'string', default
= '32kB',
342 help = "SQC cache size")
343 parser
.add_option("--sqc-assoc", type = 'int', default
= 8,
344 help = "SQC cache assoc")
345 parser
.add_option("--sqc-deadlock-threshold", type='int',
346 help="Set the SQC deadlock threshold to some value")
348 parser
.add_option("--region-dir-entries", type = "int", default
= 8192)
349 parser
.add_option("--dir-tag-latency", type = "int", default
= 8)
350 parser
.add_option("--dir-tag-banks", type = "int", default
= 4)
351 parser
.add_option("--blocks-per-region", type = "int", default
= 1)
352 parser
.add_option("--use-L3-on-WT", action
= "store_true", default
= False)
353 parser
.add_option("--nonInclusiveDir", action
= "store_true",
355 parser
.add_option("--WB_L1", action
= "store_true",
356 default
= False, help = "writeback L2")
357 parser
.add_option("--WB_L2", action
= "store_true",
358 default
= False, help = "writeback L2")
359 parser
.add_option("--TCP_latency", type = "int",
360 default
= 4, help = "TCP latency")
361 parser
.add_option("--TCC_latency", type = "int",
362 default
= 16, help = "TCC latency")
363 parser
.add_option("--tcc-size", type = 'string', default
= '2MB',
364 help = "agregate tcc size")
365 parser
.add_option("--tcc-assoc", type = 'int', default
= 16,
367 parser
.add_option("--tcp-size", type = 'string', default
= '16kB',
369 parser
.add_option("--tcp-deadlock-threshold", type='int',
370 help="Set the TCP deadlock threshold to some value")
371 parser
.add_option("--max-coalesces-per-cycle", type="int", default
=1,
372 help="Maximum insts that may coalesce in a cycle");
374 parser
.add_option("--sampler-sets", type = "int", default
= 1024)
375 parser
.add_option("--sampler-assoc", type = "int", default
= 16)
376 parser
.add_option("--sampler-counter", type = "int", default
= 512)
377 parser
.add_option("--noL1", action
= "store_true", default
= False,
379 parser
.add_option("--noL2", action
= "store_true", default
= False,
382 def create_system(options
, full_system
, system
, dma_devices
, bootmem
,
384 if buildEnv
['PROTOCOL'] != 'GPU_VIPER_Baseline':
385 panic("This script requires the" \
386 "GPU_VIPER_Baseline protocol to be built.")
391 # The ruby network creation expects the list of nodes in the system to be
392 # consistent with the NetDest list. Therefore the l1 controller nodes
393 # must be listed before the directory nodes and directory nodes before
404 # Must create the individual controllers before the network to ensure the
405 # controller constructors are called before the network constructor
408 # For an odd number of CPUs, still create the right number of controllers
409 TCC_bits
= int(math
.log(options
.num_tccs
, 2))
411 # This is the base crossbar that connects the L3s, Dirs, and cpu/gpu
413 crossbar_bw
= 16 * options
.num_compute_units
#Assuming a 2GHz clock
414 mainCluster
= Cluster(intBW
= crossbar_bw
)
416 if options
.numa_high_bit
:
417 numa_bit
= options
.numa_high_bit
419 # if the numa_bit is not specified, set the directory bits as the
420 # lowest bits above the block offset bits, and the numa_bit as the
421 # highest of those directory bits
422 dir_bits
= int(math
.log(options
.num_dirs
, 2))
423 block_size_bits
= int(math
.log(options
.cacheline_size
, 2))
424 numa_bit
= block_size_bits
+ dir_bits
- 1
426 for i
in range(options
.num_dirs
):
428 for r
in system
.mem_ranges
:
429 addr_range
= m5
.objects
.AddrRange(r
.start
, size
= r
.size(),
430 intlvHighBit
= numa_bit
,
431 intlvBits
= dir_bits
,
433 dir_ranges
.append(addr_range
)
435 dir_cntrl
= DirCntrl(noTCCdir
=True,TCC_select_num_bits
= TCC_bits
)
436 dir_cntrl
.create(options
, dir_ranges
, ruby_system
, system
)
437 dir_cntrl
.number_of_TBEs
= options
.num_tbes
438 dir_cntrl
.useL3OnWT
= options
.use_L3_on_WT
439 dir_cntrl
.inclusiveDir
= not options
.nonInclusiveDir
441 # Connect the Directory controller to the ruby network
442 dir_cntrl
.requestFromCores
= MessageBuffer(ordered
= True)
443 dir_cntrl
.requestFromCores
.slave
= ruby_system
.network
.master
445 dir_cntrl
.responseFromCores
= MessageBuffer()
446 dir_cntrl
.responseFromCores
.slave
= ruby_system
.network
.master
448 dir_cntrl
.unblockFromCores
= MessageBuffer()
449 dir_cntrl
.unblockFromCores
.slave
= ruby_system
.network
.master
451 dir_cntrl
.probeToCore
= MessageBuffer()
452 dir_cntrl
.probeToCore
.master
= ruby_system
.network
.slave
454 dir_cntrl
.responseToCore
= MessageBuffer()
455 dir_cntrl
.responseToCore
.master
= ruby_system
.network
.slave
457 dir_cntrl
.triggerQueue
= MessageBuffer(ordered
= True)
458 dir_cntrl
.L3triggerQueue
= MessageBuffer(ordered
= True)
459 dir_cntrl
.requestToMemory
= MessageBuffer()
460 dir_cntrl
.responseFromMemory
= MessageBuffer()
462 exec("system.dir_cntrl%d = dir_cntrl" % i
)
463 dir_cntrl_nodes
.append(dir_cntrl
)
464 mainCluster
.add(dir_cntrl
)
466 cpuCluster
= Cluster(extBW
= crossbar_bw
, intBW
=crossbar_bw
)
467 for i
in range((options
.num_cpus
+ 1) // 2):
470 cp_cntrl
.create(options
, ruby_system
, system
)
472 exec("system.cp_cntrl%d = cp_cntrl" % i
)
474 # Add controllers and sequencers to the appropriate lists
476 cpu_sequencers
.extend([cp_cntrl
.sequencer
, cp_cntrl
.sequencer1
])
478 # Connect the CP controllers and the network
479 cp_cntrl
.requestFromCore
= MessageBuffer()
480 cp_cntrl
.requestFromCore
.master
= ruby_system
.network
.slave
482 cp_cntrl
.responseFromCore
= MessageBuffer()
483 cp_cntrl
.responseFromCore
.master
= ruby_system
.network
.slave
485 cp_cntrl
.unblockFromCore
= MessageBuffer()
486 cp_cntrl
.unblockFromCore
.master
= ruby_system
.network
.slave
488 cp_cntrl
.probeToCore
= MessageBuffer()
489 cp_cntrl
.probeToCore
.slave
= ruby_system
.network
.master
491 cp_cntrl
.responseToCore
= MessageBuffer()
492 cp_cntrl
.responseToCore
.slave
= ruby_system
.network
.master
494 cp_cntrl
.mandatoryQueue
= MessageBuffer()
495 cp_cntrl
.triggerQueue
= MessageBuffer(ordered
= True)
497 cpuCluster
.add(cp_cntrl
)
499 gpuCluster
= Cluster(extBW
= crossbar_bw
, intBW
= crossbar_bw
)
500 for i
in range(options
.num_compute_units
):
502 tcp_cntrl
= TCPCntrl(TCC_select_num_bits
= TCC_bits
,
504 number_of_TBEs
= 2560)
505 # TBEs set to max outstanding requests
506 tcp_cntrl
.create(options
, ruby_system
, system
)
507 tcp_cntrl
.WB
= options
.WB_L1
508 tcp_cntrl
.disableL1
= options
.noL1
510 exec("system.tcp_cntrl%d = tcp_cntrl" % i
)
512 # Add controllers and sequencers to the appropriate lists
514 cpu_sequencers
.append(tcp_cntrl
.coalescer
)
515 tcp_cntrl_nodes
.append(tcp_cntrl
)
517 # Connect the CP (TCP) controllers to the ruby network
518 tcp_cntrl
.requestFromTCP
= MessageBuffer(ordered
= True)
519 tcp_cntrl
.requestFromTCP
.master
= ruby_system
.network
.slave
521 tcp_cntrl
.responseFromTCP
= MessageBuffer(ordered
= True)
522 tcp_cntrl
.responseFromTCP
.master
= ruby_system
.network
.slave
524 tcp_cntrl
.unblockFromCore
= MessageBuffer()
525 tcp_cntrl
.unblockFromCore
.master
= ruby_system
.network
.slave
527 tcp_cntrl
.probeToTCP
= MessageBuffer(ordered
= True)
528 tcp_cntrl
.probeToTCP
.slave
= ruby_system
.network
.master
530 tcp_cntrl
.responseToTCP
= MessageBuffer(ordered
= True)
531 tcp_cntrl
.responseToTCP
.slave
= ruby_system
.network
.master
533 tcp_cntrl
.mandatoryQueue
= MessageBuffer()
535 gpuCluster
.add(tcp_cntrl
)
537 for i
in range(options
.num_sqc
):
539 sqc_cntrl
= SQCCntrl(TCC_select_num_bits
= TCC_bits
)
540 sqc_cntrl
.create(options
, ruby_system
, system
)
542 exec("system.sqc_cntrl%d = sqc_cntrl" % i
)
544 # Add controllers and sequencers to the appropriate lists
546 cpu_sequencers
.append(sqc_cntrl
.sequencer
)
548 # Connect the SQC controller to the ruby network
549 sqc_cntrl
.requestFromSQC
= MessageBuffer(ordered
= True)
550 sqc_cntrl
.requestFromSQC
.master
= ruby_system
.network
.slave
552 sqc_cntrl
.probeToSQC
= MessageBuffer(ordered
= True)
553 sqc_cntrl
.probeToSQC
.slave
= ruby_system
.network
.master
555 sqc_cntrl
.responseToSQC
= MessageBuffer(ordered
= True)
556 sqc_cntrl
.responseToSQC
.slave
= ruby_system
.network
.master
558 sqc_cntrl
.mandatoryQueue
= MessageBuffer()
560 # SQC also in GPU cluster
561 gpuCluster
.add(sqc_cntrl
)
563 # Because of wire buffers, num_tccs must equal num_tccdirs
566 for i
in range(options
.num_tccs
):
568 tcc_cntrl
= TCCCntrl()
569 tcc_cntrl
.create(options
, ruby_system
, system
)
570 tcc_cntrl
.l2_request_latency
= options
.gpu_to_dir_latency
571 tcc_cntrl
.l2_response_latency
= options
.TCC_latency
572 tcc_cntrl_nodes
.append(tcc_cntrl
)
573 tcc_cntrl
.WB
= options
.WB_L2
574 tcc_cntrl
.number_of_TBEs
= 2560 * options
.num_compute_units
576 # Connect the TCC controllers to the ruby network
577 tcc_cntrl
.requestFromTCP
= MessageBuffer(ordered
= True)
578 tcc_cntrl
.requestFromTCP
.slave
= ruby_system
.network
.master
580 tcc_cntrl
.responseToCore
= MessageBuffer(ordered
= True)
581 tcc_cntrl
.responseToCore
.master
= ruby_system
.network
.slave
583 tcc_cntrl
.probeFromNB
= MessageBuffer()
584 tcc_cntrl
.probeFromNB
.slave
= ruby_system
.network
.master
586 tcc_cntrl
.responseFromNB
= MessageBuffer()
587 tcc_cntrl
.responseFromNB
.slave
= ruby_system
.network
.master
589 tcc_cntrl
.requestToNB
= MessageBuffer(ordered
= True)
590 tcc_cntrl
.requestToNB
.master
= ruby_system
.network
.slave
592 tcc_cntrl
.responseToNB
= MessageBuffer()
593 tcc_cntrl
.responseToNB
.master
= ruby_system
.network
.slave
595 tcc_cntrl
.unblockToNB
= MessageBuffer()
596 tcc_cntrl
.unblockToNB
.master
= ruby_system
.network
.slave
598 tcc_cntrl
.triggerQueue
= MessageBuffer(ordered
= True)
600 exec("system.tcc_cntrl%d = tcc_cntrl" % i
)
601 # connect all of the wire buffers between L3 and dirs up
602 # TCC cntrls added to the GPU cluster
603 gpuCluster
.add(tcc_cntrl
)
605 # Assuming no DMA devices
606 assert(len(dma_devices
) == 0)
608 # Add cpu/gpu clusters to main cluster
609 mainCluster
.add(cpuCluster
)
610 mainCluster
.add(gpuCluster
)
612 ruby_system
.network
.number_of_virtual_networks
= 10
614 return (cpu_sequencers
, dir_cntrl_nodes
, mainCluster
)