1 # Copyright (c) 2015 Advanced Micro Devices, Inc.
4 # For use for simulation and test purposes only
6 # Redistribution and use in source and binary forms, with or without
7 # modification, are permitted provided that the following conditions are met:
9 # 1. Redistributions of source code must retain the above copyright notice,
10 # this list of conditions and the following disclaimer.
12 # 2. Redistributions in binary form must reproduce the above copyright notice,
13 # this list of conditions and the following disclaimer in the documentation
14 # and/or other materials provided with the distribution.
16 # 3. Neither the name of the copyright holder nor the names of its
17 # contributors may be used to endorse or promote products derived from this
18 # software without specific prior written permission.
20 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
24 # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 # POSSIBILITY OF SUCH DAMAGE.
32 # Authors: Sooraj Puthoor
36 from m5
.objects
import *
37 from m5
.defines
import buildEnv
38 from m5
.util
import addToPath
39 from Ruby
import send_evicts
43 from topologies
.Cluster
import Cluster
49 # Use SeqCount not class since we need global count
51 return CntrlBase
._seqs
- 1
56 # Use CntlCount not class since we need global count
57 CntrlBase
._cntrls
+= 1
58 return CntrlBase
._cntrls
- 1
62 def versionCount(cls
):
63 cls
._version
+= 1 # Use count for this particular type
64 return cls
._version
- 1
67 # Note: the L1 Cache latency is only used by the sequencer on fast path hits
69 class L1Cache(RubyCache
):
70 resourceStalls
= False
75 def create(self
, size
, assoc
, options
):
76 self
.size
= MemorySize(size
)
78 self
.replacement_policy
= TreePLRURP()
80 class L2Cache(RubyCache
):
81 resourceStalls
= False
85 def create(self
, size
, assoc
, options
):
86 self
.size
= MemorySize(size
)
88 self
.replacement_policy
= TreePLRURP()
90 class CPCntrl(CorePair_Controller
, CntrlBase
):
92 def create(self
, options
, ruby_system
, system
):
93 self
.version
= self
.versionCount()
95 self
.L1Icache
= L1Cache()
96 self
.L1Icache
.create(options
.l1i_size
, options
.l1i_assoc
, options
)
97 self
.L1D0cache
= L1Cache()
98 self
.L1D0cache
.create(options
.l1d_size
, options
.l1d_assoc
, options
)
99 self
.L1D1cache
= L1Cache()
100 self
.L1D1cache
.create(options
.l1d_size
, options
.l1d_assoc
, options
)
101 self
.L2cache
= L2Cache()
102 self
.L2cache
.create(options
.l2_size
, options
.l2_assoc
, options
)
104 self
.sequencer
= RubySequencer()
105 self
.sequencer
.version
= self
.seqCount()
106 self
.sequencer
.icache
= self
.L1Icache
107 self
.sequencer
.dcache
= self
.L1D0cache
108 self
.sequencer
.ruby_system
= ruby_system
109 self
.sequencer
.coreid
= 0
110 self
.sequencer
.is_cpu_sequencer
= True
112 self
.sequencer1
= RubySequencer()
113 self
.sequencer1
.version
= self
.seqCount()
114 self
.sequencer1
.icache
= self
.L1Icache
115 self
.sequencer1
.dcache
= self
.L1D1cache
116 self
.sequencer1
.ruby_system
= ruby_system
117 self
.sequencer1
.coreid
= 1
118 self
.sequencer1
.is_cpu_sequencer
= True
120 self
.issue_latency
= 1
121 self
.send_evictions
= send_evicts(options
)
123 self
.ruby_system
= ruby_system
125 if options
.recycle_latency
:
126 self
.recycle_latency
= options
.recycle_latency
128 class TCPCache(RubyCache
):
133 dataAccessLatency
= 4
135 def create(self
, options
):
136 self
.size
= MemorySize(options
.tcp_size
)
137 self
.dataArrayBanks
= 16
138 self
.tagArrayBanks
= 16
139 self
.dataAccessLatency
= 4
140 self
.tagAccessLatency
= 1
141 self
.resourceStalls
= options
.no_tcc_resource_stalls
142 self
.replacement_policy
= TreePLRURP(num_leaves
= self
.assoc
)
144 class TCPCntrl(TCP_Controller
, CntrlBase
):
146 def create(self
, options
, ruby_system
, system
):
147 self
.version
= self
.versionCount()
148 self
.L1cache
= TCPCache(dataAccessLatency
= options
.TCP_latency
)
149 self
.L1cache
.create(options
)
150 self
.issue_latency
= 1
152 self
.coalescer
= VIPERCoalescer()
153 self
.coalescer
.version
= self
.seqCount()
154 self
.coalescer
.icache
= self
.L1cache
155 self
.coalescer
.dcache
= self
.L1cache
156 self
.coalescer
.ruby_system
= ruby_system
157 self
.coalescer
.support_inst_reqs
= False
158 self
.coalescer
.is_cpu_sequencer
= False
160 self
.sequencer
= RubySequencer()
161 self
.sequencer
.version
= self
.seqCount()
162 self
.sequencer
.icache
= self
.L1cache
163 self
.sequencer
.dcache
= self
.L1cache
164 self
.sequencer
.ruby_system
= ruby_system
165 self
.sequencer
.is_cpu_sequencer
= True
167 self
.use_seq_not_coal
= False
169 self
.ruby_system
= ruby_system
170 if options
.recycle_latency
:
171 self
.recycle_latency
= options
.recycle_latency
173 class SQCCache(RubyCache
):
176 dataAccessLatency
= 1
179 def create(self
, options
):
180 self
.size
= MemorySize(options
.sqc_size
)
181 self
.assoc
= options
.sqc_assoc
182 self
.replacement_policy
= TreePLRURP(num_leaves
= self
.assoc
)
184 class SQCCntrl(SQC_Controller
, CntrlBase
):
186 def create(self
, options
, ruby_system
, system
):
187 self
.version
= self
.versionCount()
188 self
.L1cache
= SQCCache()
189 self
.L1cache
.create(options
)
190 self
.L1cache
.resourceStalls
= False
191 self
.sequencer
= RubySequencer()
192 self
.sequencer
.version
= self
.seqCount()
193 self
.sequencer
.icache
= self
.L1cache
194 self
.sequencer
.dcache
= self
.L1cache
195 self
.sequencer
.ruby_system
= ruby_system
196 self
.sequencer
.support_data_reqs
= False
197 self
.sequencer
.is_cpu_sequencer
= False
198 self
.ruby_system
= ruby_system
199 if options
.recycle_latency
:
200 self
.recycle_latency
= options
.recycle_latency
202 class TCC(RubyCache
):
203 size
= MemorySize("256kB")
205 dataAccessLatency
= 8
207 resourceStalls
= False
208 def create(self
, options
):
209 self
.assoc
= options
.tcc_assoc
210 if hasattr(options
, 'bw_scalor') and options
.bw_scalor
> 0:
211 s
= options
.num_compute_units
213 tcc_size
= str(tcc_size
)+'kB'
214 self
.size
= MemorySize(tcc_size
)
215 self
.dataArrayBanks
= 64
216 self
.tagArrayBanks
= 64
218 self
.size
= MemorySize(options
.tcc_size
)
219 self
.dataArrayBanks
= 256 / options
.num_tccs
#number of data banks
220 self
.tagArrayBanks
= 256 / options
.num_tccs
#number of tag banks
221 self
.size
.value
= self
.size
.value
/ options
.num_tccs
222 if ((self
.size
.value
/ long(self
.assoc
)) < 128):
223 self
.size
.value
= long(128 * self
.assoc
)
224 self
.start_index_bit
= math
.log(options
.cacheline_size
, 2) + \
225 math
.log(options
.num_tccs
, 2)
226 self
.replacement_policy
= TreePLRURP(num_leaves
= self
.assoc
)
228 class TCCCntrl(TCC_Controller
, CntrlBase
):
229 def create(self
, options
, ruby_system
, system
):
230 self
.version
= self
.versionCount()
232 self
.L2cache
.create(options
)
233 self
.ruby_system
= ruby_system
234 if options
.recycle_latency
:
235 self
.recycle_latency
= options
.recycle_latency
237 class L3Cache(RubyCache
):
241 def create(self
, options
, ruby_system
, system
):
242 self
.size
= MemorySize(options
.l3_size
)
243 self
.size
.value
/= options
.num_dirs
244 self
.assoc
= options
.l3_assoc
245 self
.dataArrayBanks
/= options
.num_dirs
246 self
.tagArrayBanks
/= options
.num_dirs
247 self
.dataArrayBanks
/= options
.num_dirs
248 self
.tagArrayBanks
/= options
.num_dirs
249 self
.dataAccessLatency
= options
.l3_data_latency
250 self
.tagAccessLatency
= options
.l3_tag_latency
251 self
.resourceStalls
= False
252 self
.replacement_policy
= TreePLRURP(num_leaves
= self
.assoc
)
254 class L3Cntrl(L3Cache_Controller
, CntrlBase
):
255 def create(self
, options
, ruby_system
, system
):
256 self
.version
= self
.versionCount()
257 self
.L3cache
= L3Cache()
258 self
.L3cache
.create(options
, ruby_system
, system
)
259 self
.l3_response_latency
= \
260 max(self
.L3cache
.dataAccessLatency
, self
.L3cache
.tagAccessLatency
)
261 self
.ruby_system
= ruby_system
262 if options
.recycle_latency
:
263 self
.recycle_latency
= options
.recycle_latency
265 def connectWireBuffers(self
, req_to_dir
, resp_to_dir
, l3_unblock_to_dir
,
266 req_to_l3
, probe_to_l3
, resp_to_l3
):
267 self
.reqToDir
= req_to_dir
268 self
.respToDir
= resp_to_dir
269 self
.l3UnblockToDir
= l3_unblock_to_dir
270 self
.reqToL3
= req_to_l3
271 self
.probeToL3
= probe_to_l3
272 self
.respToL3
= resp_to_l3
274 # Directory memory: Directory memory of infinite size which is
275 # used by directory controller to store the "states" of the
276 # state machine. The state machine is implemented per cache block
277 class DirMem(RubyDirectoryMemory
, CntrlBase
):
278 def create(self
, options
, ruby_system
, system
):
279 self
.version
= self
.versionCount()
280 phys_mem_size
= AddrRange(options
.mem_size
).size()
281 mem_module_size
= phys_mem_size
/ options
.num_dirs
282 dir_size
= MemorySize('0B')
283 dir_size
.value
= mem_module_size
286 # Directory controller: Contains directory memory, L3 cache and associated state
287 # machine which is used to accurately redirect a data request to L3 cache or to
288 # memory. The permissions requests do not come to this directory for region
289 # based protocols as they are handled exclusively by the region directory.
290 # However, region directory controller uses this directory controller for
291 # sending probe requests and receiving probe responses.
292 class DirCntrl(Directory_Controller
, CntrlBase
):
293 def create(self
, options
, ruby_system
, system
):
294 self
.version
= self
.versionCount()
295 self
.response_latency
= 25
296 self
.response_latency_regionDir
= 1
297 self
.directory
= DirMem()
298 self
.directory
.create(options
, ruby_system
, system
)
299 self
.L3CacheMemory
= L3Cache()
300 self
.L3CacheMemory
.create(options
, ruby_system
, system
)
301 self
.l3_hit_latency
= \
302 max(self
.L3CacheMemory
.dataAccessLatency
,
303 self
.L3CacheMemory
.tagAccessLatency
)
305 self
.ruby_system
= ruby_system
306 if options
.recycle_latency
:
307 self
.recycle_latency
= options
.recycle_latency
309 def connectWireBuffers(self
, req_to_dir
, resp_to_dir
, l3_unblock_to_dir
,
310 req_to_l3
, probe_to_l3
, resp_to_l3
):
311 self
.reqToDir
= req_to_dir
312 self
.respToDir
= resp_to_dir
313 self
.l3UnblockToDir
= l3_unblock_to_dir
314 self
.reqToL3
= req_to_l3
315 self
.probeToL3
= probe_to_l3
316 self
.respToL3
= resp_to_l3
318 # Region directory : Stores region permissions
319 class RegionDir(RubyCache
):
321 def create(self
, options
, ruby_system
, system
):
322 self
.block_size
= "%dB" % (64 * options
.blocks_per_region
)
323 self
.size
= options
.region_dir_entries
* \
324 self
.block_size
* options
.num_compute_units
326 self
.tagArrayBanks
= 8
327 self
.tagAccessLatency
= options
.dir_tag_latency
328 self
.dataAccessLatency
= 1
329 self
.resourceStalls
= options
.no_resource_stalls
330 self
.start_index_bit
= 6 + int(math
.log(options
.blocks_per_region
, 2))
331 self
.replacement_policy
= TreePLRURP(num_leaves
= self
.assoc
)
332 # Region directory controller : Contains region directory and associated state
333 # machine for dealing with region coherence requests.
334 class RegionCntrl(RegionDir_Controller
, CntrlBase
):
335 def create(self
, options
, ruby_system
, system
):
336 self
.version
= self
.versionCount()
337 self
.cacheMemory
= RegionDir()
338 self
.cacheMemory
.create(options
, ruby_system
, system
)
339 self
.blocksPerRegion
= options
.blocks_per_region
340 self
.toDirLatency
= \
341 max(self
.cacheMemory
.dataAccessLatency
,
342 self
.cacheMemory
.tagAccessLatency
)
343 self
.ruby_system
= ruby_system
344 self
.always_migrate
= options
.always_migrate
345 self
.sym_migrate
= options
.symmetric_migrate
346 self
.asym_migrate
= options
.asymmetric_migrate
347 if self
.always_migrate
:
348 assert(not self
.asym_migrate
and not self
.sym_migrate
)
350 assert(not self
.always_migrate
and not self
.asym_migrate
)
351 if self
.asym_migrate
:
352 assert(not self
.always_migrate
and not self
.sym_migrate
)
353 if options
.recycle_latency
:
354 self
.recycle_latency
= options
.recycle_latency
356 # Region Buffer: A region directory cache which avoids some potential
357 # long latency lookup of region directory for getting region permissions
358 class RegionBuffer(RubyCache
):
362 dataAccessLatency
= 1
364 resourceStalls
= True
366 class RBCntrl(RegionBuffer_Controller
, CntrlBase
):
367 def create(self
, options
, ruby_system
, system
):
368 self
.version
= self
.versionCount()
369 self
.cacheMemory
= RegionBuffer()
370 self
.cacheMemory
.resourceStalls
= options
.no_tcc_resource_stalls
371 self
.cacheMemory
.dataArrayBanks
= 64
372 self
.cacheMemory
.tagArrayBanks
= 64
373 self
.blocksPerRegion
= options
.blocks_per_region
374 self
.cacheMemory
.block_size
= "%dB" % (64 * self
.blocksPerRegion
)
375 self
.cacheMemory
.start_index_bit
= \
376 6 + int(math
.log(self
.blocksPerRegion
, 2))
377 self
.cacheMemory
.size
= options
.region_buffer_entries
* \
378 self
.cacheMemory
.block_size
* options
.num_compute_units
379 self
.toDirLatency
= options
.gpu_to_dir_latency
380 self
.toRegionDirLatency
= options
.cpu_to_dir_latency
382 TCC_bits
= int(math
.log(options
.num_tccs
, 2))
383 self
.TCC_select_num_bits
= TCC_bits
384 self
.ruby_system
= ruby_system
386 if options
.recycle_latency
:
387 self
.recycle_latency
= options
.recycle_latency
388 self
.cacheMemory
.replacement_policy
= \
389 TreePLRURP(num_leaves
= self
.cacheMemory
.assoc
)
391 def define_options(parser
):
392 parser
.add_option("--num-subcaches", type="int", default
=4)
393 parser
.add_option("--l3-data-latency", type="int", default
=20)
394 parser
.add_option("--l3-tag-latency", type="int", default
=15)
395 parser
.add_option("--cpu-to-dir-latency", type="int", default
=120)
396 parser
.add_option("--gpu-to-dir-latency", type="int", default
=60)
397 parser
.add_option("--no-resource-stalls", action
="store_false",
399 parser
.add_option("--no-tcc-resource-stalls", action
="store_false",
401 parser
.add_option("--num-tbes", type="int", default
=32)
402 parser
.add_option("--l2-latency", type="int", default
=50) # load to use
403 parser
.add_option("--num-tccs", type="int", default
=1,
404 help="number of TCC banks in the GPU")
406 parser
.add_option("--sqc-size", type='string', default
='32kB',
407 help="SQC cache size")
408 parser
.add_option("--sqc-assoc", type='int', default
=8,
409 help="SQC cache assoc")
411 parser
.add_option("--WB_L1", action
="store_true",
412 default
=False, help="L2 Writeback Cache")
413 parser
.add_option("--WB_L2", action
="store_true",
414 default
=False, help="L2 Writeback Cache")
415 parser
.add_option("--TCP_latency",
416 type="int", default
=4, help="TCP latency")
417 parser
.add_option("--TCC_latency",
418 type="int", default
=16, help="TCC latency")
419 parser
.add_option("--tcc-size", type='string', default
='2MB',
420 help="agregate tcc size")
421 parser
.add_option("--tcc-assoc", type='int', default
=16,
423 parser
.add_option("--tcp-size", type='string', default
='16kB',
426 parser
.add_option("--dir-tag-latency", type="int", default
=4)
427 parser
.add_option("--dir-tag-banks", type="int", default
=4)
428 parser
.add_option("--blocks-per-region", type="int", default
=16)
429 parser
.add_option("--dir-entries", type="int", default
=8192)
431 # Region buffer is a cache of region directory. Hence region
432 # directory is inclusive with respect to region directory.
433 # However, region directory is non-inclusive with respect to
434 # the caches in the system
435 parser
.add_option("--region-dir-entries", type="int", default
=1024)
436 parser
.add_option("--region-buffer-entries", type="int", default
=512)
438 parser
.add_option("--always-migrate",
439 action
="store_true", default
=False)
440 parser
.add_option("--symmetric-migrate",
441 action
="store_true", default
=False)
442 parser
.add_option("--asymmetric-migrate",
443 action
="store_true", default
=False)
444 parser
.add_option("--use-L3-on-WT", action
="store_true", default
=False)
446 def create_system(options
, full_system
, system
, dma_devices
, bootmem
,
448 if buildEnv
['PROTOCOL'] != 'GPU_VIPER_Region':
449 panic("This script requires the GPU_VIPER_Region protocol to be built.")
454 # The ruby network creation expects the list of nodes in the system to be
455 # consistent with the NetDest list. Therefore the l1 controller nodes
456 # must be listed before the directory nodes and directory nodes before
461 # For an odd number of CPUs, still create the right number of controllers
462 TCC_bits
= int(math
.log(options
.num_tccs
, 2))
465 # Must create the individual controllers before the network to ensure the
466 # controller constructors are called before the network constructor
469 # For an odd number of CPUs, still create the right number of controllers
470 crossbar_bw
= 16 * options
.num_compute_units
#Assuming a 2GHz clock
471 cpuCluster
= Cluster(extBW
= (crossbar_bw
), intBW
=crossbar_bw
)
472 for i
in range((options
.num_cpus
+ 1) // 2):
475 cp_cntrl
.create(options
, ruby_system
, system
)
478 rb_cntrl
.create(options
, ruby_system
, system
)
479 rb_cntrl
.number_of_TBEs
= 256
480 rb_cntrl
.isOnCPU
= True
482 cp_cntrl
.regionBufferNum
= rb_cntrl
.version
484 exec("system.cp_cntrl%d = cp_cntrl" % i
)
485 exec("system.rb_cntrl%d = rb_cntrl" % i
)
487 # Add controllers and sequencers to the appropriate lists
489 cpu_sequencers
.extend([cp_cntrl
.sequencer
, cp_cntrl
.sequencer1
])
491 # Connect the CP controllers and the network
492 cp_cntrl
.requestFromCore
= MessageBuffer()
493 cp_cntrl
.requestFromCore
.master
= ruby_system
.network
.slave
495 cp_cntrl
.responseFromCore
= MessageBuffer()
496 cp_cntrl
.responseFromCore
.master
= ruby_system
.network
.slave
498 cp_cntrl
.unblockFromCore
= MessageBuffer()
499 cp_cntrl
.unblockFromCore
.master
= ruby_system
.network
.slave
501 cp_cntrl
.probeToCore
= MessageBuffer()
502 cp_cntrl
.probeToCore
.slave
= ruby_system
.network
.master
504 cp_cntrl
.responseToCore
= MessageBuffer()
505 cp_cntrl
.responseToCore
.slave
= ruby_system
.network
.master
507 cp_cntrl
.mandatoryQueue
= MessageBuffer()
508 cp_cntrl
.triggerQueue
= MessageBuffer(ordered
= True)
510 # Connect the RB controllers to the ruby network
511 rb_cntrl
.requestFromCore
= MessageBuffer(ordered
= True)
512 rb_cntrl
.requestFromCore
.slave
= ruby_system
.network
.master
514 rb_cntrl
.responseFromCore
= MessageBuffer()
515 rb_cntrl
.responseFromCore
.slave
= ruby_system
.network
.master
517 rb_cntrl
.requestToNetwork
= MessageBuffer()
518 rb_cntrl
.requestToNetwork
.master
= ruby_system
.network
.slave
520 rb_cntrl
.notifyFromRegionDir
= MessageBuffer()
521 rb_cntrl
.notifyFromRegionDir
.slave
= ruby_system
.network
.master
523 rb_cntrl
.probeFromRegionDir
= MessageBuffer()
524 rb_cntrl
.probeFromRegionDir
.slave
= ruby_system
.network
.master
526 rb_cntrl
.unblockFromDir
= MessageBuffer()
527 rb_cntrl
.unblockFromDir
.slave
= ruby_system
.network
.master
529 rb_cntrl
.responseToRegDir
= MessageBuffer()
530 rb_cntrl
.responseToRegDir
.master
= ruby_system
.network
.slave
532 rb_cntrl
.triggerQueue
= MessageBuffer(ordered
= True)
534 cpuCluster
.add(cp_cntrl
)
535 cpuCluster
.add(rb_cntrl
)
537 gpuCluster
= Cluster(extBW
= (crossbar_bw
), intBW
= crossbar_bw
)
538 for i
in range(options
.num_compute_units
):
540 tcp_cntrl
= TCPCntrl(TCC_select_num_bits
= TCC_bits
,
542 number_of_TBEs
= 2560)
543 # TBEs set to max outstanding requests
544 tcp_cntrl
.create(options
, ruby_system
, system
)
545 tcp_cntrl
.WB
= options
.WB_L1
546 tcp_cntrl
.disableL1
= False
548 exec("system.tcp_cntrl%d = tcp_cntrl" % i
)
550 # Add controllers and sequencers to the appropriate lists
552 cpu_sequencers
.append(tcp_cntrl
.coalescer
)
554 # Connect the CP (TCP) controllers to the ruby network
555 tcp_cntrl
.requestFromTCP
= MessageBuffer(ordered
= True)
556 tcp_cntrl
.requestFromTCP
.master
= ruby_system
.network
.slave
558 tcp_cntrl
.responseFromTCP
= MessageBuffer(ordered
= True)
559 tcp_cntrl
.responseFromTCP
.master
= ruby_system
.network
.slave
561 tcp_cntrl
.unblockFromCore
= MessageBuffer()
562 tcp_cntrl
.unblockFromCore
.master
= ruby_system
.network
.slave
564 tcp_cntrl
.probeToTCP
= MessageBuffer(ordered
= True)
565 tcp_cntrl
.probeToTCP
.slave
= ruby_system
.network
.master
567 tcp_cntrl
.responseToTCP
= MessageBuffer(ordered
= True)
568 tcp_cntrl
.responseToTCP
.slave
= ruby_system
.network
.master
570 tcp_cntrl
.mandatoryQueue
= MessageBuffer()
572 gpuCluster
.add(tcp_cntrl
)
574 for i
in range(options
.num_sqc
):
576 sqc_cntrl
= SQCCntrl(TCC_select_num_bits
= TCC_bits
)
577 sqc_cntrl
.create(options
, ruby_system
, system
)
579 exec("system.sqc_cntrl%d = sqc_cntrl" % i
)
581 # Add controllers and sequencers to the appropriate lists
583 cpu_sequencers
.append(sqc_cntrl
.sequencer
)
585 # Connect the SQC controller to the ruby network
586 sqc_cntrl
.requestFromSQC
= MessageBuffer(ordered
= True)
587 sqc_cntrl
.requestFromSQC
.master
= ruby_system
.network
.slave
589 sqc_cntrl
.probeToSQC
= MessageBuffer(ordered
= True)
590 sqc_cntrl
.probeToSQC
.slave
= ruby_system
.network
.master
592 sqc_cntrl
.responseToSQC
= MessageBuffer(ordered
= True)
593 sqc_cntrl
.responseToSQC
.slave
= ruby_system
.network
.master
595 sqc_cntrl
.mandatoryQueue
= MessageBuffer()
597 # SQC also in GPU cluster
598 gpuCluster
.add(sqc_cntrl
)
602 for i
in range(options
.num_tccs
):
604 tcc_cntrl
= TCCCntrl()
605 tcc_cntrl
.create(options
, ruby_system
, system
)
606 tcc_cntrl
.l2_request_latency
= 1
607 tcc_cntrl
.l2_response_latency
= options
.TCC_latency
608 tcc_cntrl
.WB
= options
.WB_L2
609 tcc_cntrl
.number_of_TBEs
= 2560 * options
.num_compute_units
611 # Connect the TCC controllers to the ruby network
612 tcc_cntrl
.requestFromTCP
= MessageBuffer(ordered
= True)
613 tcc_cntrl
.requestFromTCP
.slave
= ruby_system
.network
.master
615 tcc_cntrl
.responseToCore
= MessageBuffer(ordered
= True)
616 tcc_cntrl
.responseToCore
.master
= ruby_system
.network
.slave
618 tcc_cntrl
.probeFromNB
= MessageBuffer()
619 tcc_cntrl
.probeFromNB
.slave
= ruby_system
.network
.master
621 tcc_cntrl
.responseFromNB
= MessageBuffer()
622 tcc_cntrl
.responseFromNB
.slave
= ruby_system
.network
.master
624 tcc_cntrl
.requestToNB
= MessageBuffer(ordered
= True)
625 tcc_cntrl
.requestToNB
.master
= ruby_system
.network
.slave
627 tcc_cntrl
.responseToNB
= MessageBuffer()
628 tcc_cntrl
.responseToNB
.master
= ruby_system
.network
.slave
630 tcc_cntrl
.unblockToNB
= MessageBuffer()
631 tcc_cntrl
.unblockToNB
.master
= ruby_system
.network
.slave
633 tcc_cntrl
.triggerQueue
= MessageBuffer(ordered
= True)
636 rb_cntrl
.create(options
, ruby_system
, system
)
637 rb_cntrl
.number_of_TBEs
= 2560 * options
.num_compute_units
638 rb_cntrl
.isOnCPU
= False
640 # Connect the RB controllers to the ruby network
641 rb_cntrl
.requestFromCore
= MessageBuffer(ordered
= True)
642 rb_cntrl
.requestFromCore
.slave
= ruby_system
.network
.master
644 rb_cntrl
.responseFromCore
= MessageBuffer()
645 rb_cntrl
.responseFromCore
.slave
= ruby_system
.network
.master
647 rb_cntrl
.requestToNetwork
= MessageBuffer()
648 rb_cntrl
.requestToNetwork
.master
= ruby_system
.network
.slave
650 rb_cntrl
.notifyFromRegionDir
= MessageBuffer()
651 rb_cntrl
.notifyFromRegionDir
.slave
= ruby_system
.network
.master
653 rb_cntrl
.probeFromRegionDir
= MessageBuffer()
654 rb_cntrl
.probeFromRegionDir
.slave
= ruby_system
.network
.master
656 rb_cntrl
.unblockFromDir
= MessageBuffer()
657 rb_cntrl
.unblockFromDir
.slave
= ruby_system
.network
.master
659 rb_cntrl
.responseToRegDir
= MessageBuffer()
660 rb_cntrl
.responseToRegDir
.master
= ruby_system
.network
.slave
662 rb_cntrl
.triggerQueue
= MessageBuffer(ordered
= True)
664 tcc_cntrl
.regionBufferNum
= rb_cntrl
.version
666 exec("system.tcc_cntrl%d = tcc_cntrl" % i
)
667 exec("system.tcc_rb_cntrl%d = rb_cntrl" % i
)
669 # TCC cntrls added to the GPU cluster
670 gpuCluster
.add(tcc_cntrl
)
671 gpuCluster
.add(rb_cntrl
)
673 # Because of wire buffers, num_l3caches must equal num_dirs
674 # Region coherence only works with 1 dir
675 assert(options
.num_l3caches
== options
.num_dirs
== 1)
677 # This is the base crossbar that connects the L3s, Dirs, and cpu/gpu
679 mainCluster
= Cluster(intBW
= crossbar_bw
)
681 dir_cntrl
= DirCntrl()
682 dir_cntrl
.create(options
, ruby_system
, system
)
683 dir_cntrl
.number_of_TBEs
= 2560 * options
.num_compute_units
684 dir_cntrl
.useL3OnWT
= options
.use_L3_on_WT
686 # Connect the Directory controller to the ruby network
687 dir_cntrl
.requestFromCores
= MessageBuffer()
688 dir_cntrl
.requestFromCores
.slave
= ruby_system
.network
.master
690 dir_cntrl
.responseFromCores
= MessageBuffer()
691 dir_cntrl
.responseFromCores
.slave
= ruby_system
.network
.master
693 dir_cntrl
.unblockFromCores
= MessageBuffer()
694 dir_cntrl
.unblockFromCores
.slave
= ruby_system
.network
.master
696 dir_cntrl
.probeToCore
= MessageBuffer()
697 dir_cntrl
.probeToCore
.master
= ruby_system
.network
.slave
699 dir_cntrl
.responseToCore
= MessageBuffer()
700 dir_cntrl
.responseToCore
.master
= ruby_system
.network
.slave
702 dir_cntrl
.reqFromRegBuf
= MessageBuffer()
703 dir_cntrl
.reqFromRegBuf
.slave
= ruby_system
.network
.master
705 dir_cntrl
.reqToRegDir
= MessageBuffer(ordered
= True)
706 dir_cntrl
.reqToRegDir
.master
= ruby_system
.network
.slave
708 dir_cntrl
.reqFromRegDir
= MessageBuffer(ordered
= True)
709 dir_cntrl
.reqFromRegDir
.slave
= ruby_system
.network
.master
711 dir_cntrl
.unblockToRegDir
= MessageBuffer()
712 dir_cntrl
.unblockToRegDir
.master
= ruby_system
.network
.slave
714 dir_cntrl
.triggerQueue
= MessageBuffer(ordered
= True)
715 dir_cntrl
.L3triggerQueue
= MessageBuffer(ordered
= True)
716 dir_cntrl
.responseFromMemory
= MessageBuffer()
718 exec("system.dir_cntrl%d = dir_cntrl" % i
)
719 dir_cntrl_nodes
.append(dir_cntrl
)
721 mainCluster
.add(dir_cntrl
)
723 reg_cntrl
= RegionCntrl(noTCCdir
=True,TCC_select_num_bits
= TCC_bits
)
724 reg_cntrl
.create(options
, ruby_system
, system
)
725 reg_cntrl
.number_of_TBEs
= options
.num_tbes
726 reg_cntrl
.cpuRegionBufferNum
= system
.rb_cntrl0
.version
727 reg_cntrl
.gpuRegionBufferNum
= system
.tcc_rb_cntrl0
.version
729 # Connect the Region Dir controllers to the ruby network
730 reg_cntrl
.requestToDir
= MessageBuffer(ordered
= True)
731 reg_cntrl
.requestToDir
.master
= ruby_system
.network
.slave
733 reg_cntrl
.notifyToRBuffer
= MessageBuffer()
734 reg_cntrl
.notifyToRBuffer
.master
= ruby_system
.network
.slave
736 reg_cntrl
.probeToRBuffer
= MessageBuffer()
737 reg_cntrl
.probeToRBuffer
.master
= ruby_system
.network
.slave
739 reg_cntrl
.responseFromRBuffer
= MessageBuffer()
740 reg_cntrl
.responseFromRBuffer
.slave
= ruby_system
.network
.master
742 reg_cntrl
.requestFromRegBuf
= MessageBuffer()
743 reg_cntrl
.requestFromRegBuf
.slave
= ruby_system
.network
.master
745 reg_cntrl
.triggerQueue
= MessageBuffer(ordered
= True)
747 exec("system.reg_cntrl%d = reg_cntrl" % i
)
749 mainCluster
.add(reg_cntrl
)
751 # Assuming no DMA devices
752 assert(len(dma_devices
) == 0)
754 # Add cpu/gpu clusters to main cluster
755 mainCluster
.add(cpuCluster
)
756 mainCluster
.add(gpuCluster
)
758 ruby_system
.network
.number_of_virtual_networks
= 10
760 return (cpu_sequencers
, dir_cntrl_nodes
, mainCluster
)