1 # Copyright (c) 2015 Advanced Micro Devices, Inc.
4 # For use for simulation and test purposes only
6 # Redistribution and use in source and binary forms, with or without
7 # modification, are permitted provided that the following conditions are met:
9 # 1. Redistributions of source code must retain the above copyright notice,
10 # this list of conditions and the following disclaimer.
12 # 2. Redistributions in binary form must reproduce the above copyright notice,
13 # this list of conditions and the following disclaimer in the documentation
14 # and/or other materials provided with the distribution.
16 # 3. Neither the name of the copyright holder nor the names of its
17 # contributors may be used to endorse or promote products derived from this
18 # software without specific prior written permission.
20 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
24 # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 # POSSIBILITY OF SUCH DAMAGE.
34 from m5
.objects
import *
35 from m5
.defines
import buildEnv
36 from m5
.util
import addToPath
37 from Ruby
import send_evicts
41 from topologies
.Cluster
import Cluster
47 # Use SeqCount not class since we need global count
49 return CntrlBase
._seqs
- 1
54 # Use CntlCount not class since we need global count
55 CntrlBase
._cntrls
+= 1
56 return CntrlBase
._cntrls
- 1
60 def versionCount(cls
):
61 cls
._version
+= 1 # Use count for this particular type
62 return cls
._version
- 1
65 # Note: the L1 Cache latency is only used by the sequencer on fast path hits
67 class L1Cache(RubyCache
):
68 resourceStalls
= False
73 def create(self
, size
, assoc
, options
):
74 self
.size
= MemorySize(size
)
76 self
.replacement_policy
= TreePLRURP()
78 class L2Cache(RubyCache
):
79 resourceStalls
= False
83 def create(self
, size
, assoc
, options
):
84 self
.size
= MemorySize(size
)
86 self
.replacement_policy
= TreePLRURP()
88 class CPCntrl(CorePair_Controller
, CntrlBase
):
90 def create(self
, options
, ruby_system
, system
):
91 self
.version
= self
.versionCount()
93 self
.L1Icache
= L1Cache()
94 self
.L1Icache
.create(options
.l1i_size
, options
.l1i_assoc
, options
)
95 self
.L1D0cache
= L1Cache()
96 self
.L1D0cache
.create(options
.l1d_size
, options
.l1d_assoc
, options
)
97 self
.L1D1cache
= L1Cache()
98 self
.L1D1cache
.create(options
.l1d_size
, options
.l1d_assoc
, options
)
99 self
.L2cache
= L2Cache()
100 self
.L2cache
.create(options
.l2_size
, options
.l2_assoc
, options
)
102 self
.sequencer
= RubySequencer()
103 self
.sequencer
.version
= self
.seqCount()
104 self
.sequencer
.icache
= self
.L1Icache
105 self
.sequencer
.dcache
= self
.L1D0cache
106 self
.sequencer
.ruby_system
= ruby_system
107 self
.sequencer
.coreid
= 0
108 self
.sequencer
.is_cpu_sequencer
= True
110 self
.sequencer1
= RubySequencer()
111 self
.sequencer1
.version
= self
.seqCount()
112 self
.sequencer1
.icache
= self
.L1Icache
113 self
.sequencer1
.dcache
= self
.L1D1cache
114 self
.sequencer1
.ruby_system
= ruby_system
115 self
.sequencer1
.coreid
= 1
116 self
.sequencer1
.is_cpu_sequencer
= True
118 self
.issue_latency
= 1
119 self
.send_evictions
= send_evicts(options
)
121 self
.ruby_system
= ruby_system
123 if options
.recycle_latency
:
124 self
.recycle_latency
= options
.recycle_latency
126 class TCPCache(RubyCache
):
131 dataAccessLatency
= 4
133 def create(self
, options
):
134 self
.size
= MemorySize(options
.tcp_size
)
135 self
.dataArrayBanks
= 16
136 self
.tagArrayBanks
= 16
137 self
.dataAccessLatency
= 4
138 self
.tagAccessLatency
= 1
139 self
.resourceStalls
= options
.no_tcc_resource_stalls
140 self
.replacement_policy
= TreePLRURP(num_leaves
= self
.assoc
)
142 class TCPCntrl(TCP_Controller
, CntrlBase
):
144 def create(self
, options
, ruby_system
, system
):
145 self
.version
= self
.versionCount()
146 self
.L1cache
= TCPCache(dataAccessLatency
= options
.TCP_latency
)
147 self
.L1cache
.create(options
)
148 self
.issue_latency
= 1
150 self
.coalescer
= VIPERCoalescer()
151 self
.coalescer
.version
= self
.seqCount()
152 self
.coalescer
.icache
= self
.L1cache
153 self
.coalescer
.dcache
= self
.L1cache
154 self
.coalescer
.ruby_system
= ruby_system
155 self
.coalescer
.support_inst_reqs
= False
156 self
.coalescer
.is_cpu_sequencer
= False
158 self
.sequencer
= RubySequencer()
159 self
.sequencer
.version
= self
.seqCount()
160 self
.sequencer
.icache
= self
.L1cache
161 self
.sequencer
.dcache
= self
.L1cache
162 self
.sequencer
.ruby_system
= ruby_system
163 self
.sequencer
.is_cpu_sequencer
= True
165 self
.use_seq_not_coal
= False
167 self
.ruby_system
= ruby_system
168 if options
.recycle_latency
:
169 self
.recycle_latency
= options
.recycle_latency
171 class SQCCache(RubyCache
):
174 dataAccessLatency
= 1
177 def create(self
, options
):
178 self
.size
= MemorySize(options
.sqc_size
)
179 self
.assoc
= options
.sqc_assoc
180 self
.replacement_policy
= TreePLRURP(num_leaves
= self
.assoc
)
182 class SQCCntrl(SQC_Controller
, CntrlBase
):
184 def create(self
, options
, ruby_system
, system
):
185 self
.version
= self
.versionCount()
186 self
.L1cache
= SQCCache()
187 self
.L1cache
.create(options
)
188 self
.L1cache
.resourceStalls
= False
189 self
.sequencer
= RubySequencer()
190 self
.sequencer
.version
= self
.seqCount()
191 self
.sequencer
.icache
= self
.L1cache
192 self
.sequencer
.dcache
= self
.L1cache
193 self
.sequencer
.ruby_system
= ruby_system
194 self
.sequencer
.support_data_reqs
= False
195 self
.sequencer
.is_cpu_sequencer
= False
196 self
.ruby_system
= ruby_system
197 if options
.recycle_latency
:
198 self
.recycle_latency
= options
.recycle_latency
200 class TCC(RubyCache
):
201 size
= MemorySize("256kB")
203 dataAccessLatency
= 8
205 resourceStalls
= False
206 def create(self
, options
):
207 self
.assoc
= options
.tcc_assoc
208 if hasattr(options
, 'bw_scalor') and options
.bw_scalor
> 0:
209 s
= options
.num_compute_units
211 tcc_size
= str(tcc_size
)+'kB'
212 self
.size
= MemorySize(tcc_size
)
213 self
.dataArrayBanks
= 64
214 self
.tagArrayBanks
= 64
216 self
.size
= MemorySize(options
.tcc_size
)
217 self
.dataArrayBanks
= 256 / options
.num_tccs
#number of data banks
218 self
.tagArrayBanks
= 256 / options
.num_tccs
#number of tag banks
219 self
.size
.value
= self
.size
.value
/ options
.num_tccs
220 if ((self
.size
.value
/ long(self
.assoc
)) < 128):
221 self
.size
.value
= long(128 * self
.assoc
)
222 self
.start_index_bit
= math
.log(options
.cacheline_size
, 2) + \
223 math
.log(options
.num_tccs
, 2)
224 self
.replacement_policy
= TreePLRURP(num_leaves
= self
.assoc
)
226 class TCCCntrl(TCC_Controller
, CntrlBase
):
227 def create(self
, options
, ruby_system
, system
):
228 self
.version
= self
.versionCount()
230 self
.L2cache
.create(options
)
231 self
.ruby_system
= ruby_system
232 if options
.recycle_latency
:
233 self
.recycle_latency
= options
.recycle_latency
235 class L3Cache(RubyCache
):
239 def create(self
, options
, ruby_system
, system
):
240 self
.size
= MemorySize(options
.l3_size
)
241 self
.size
.value
/= options
.num_dirs
242 self
.assoc
= options
.l3_assoc
243 self
.dataArrayBanks
/= options
.num_dirs
244 self
.tagArrayBanks
/= options
.num_dirs
245 self
.dataArrayBanks
/= options
.num_dirs
246 self
.tagArrayBanks
/= options
.num_dirs
247 self
.dataAccessLatency
= options
.l3_data_latency
248 self
.tagAccessLatency
= options
.l3_tag_latency
249 self
.resourceStalls
= False
250 self
.replacement_policy
= TreePLRURP(num_leaves
= self
.assoc
)
252 class L3Cntrl(L3Cache_Controller
, CntrlBase
):
253 def create(self
, options
, ruby_system
, system
):
254 self
.version
= self
.versionCount()
255 self
.L3cache
= L3Cache()
256 self
.L3cache
.create(options
, ruby_system
, system
)
257 self
.l3_response_latency
= \
258 max(self
.L3cache
.dataAccessLatency
, self
.L3cache
.tagAccessLatency
)
259 self
.ruby_system
= ruby_system
260 if options
.recycle_latency
:
261 self
.recycle_latency
= options
.recycle_latency
263 def connectWireBuffers(self
, req_to_dir
, resp_to_dir
, l3_unblock_to_dir
,
264 req_to_l3
, probe_to_l3
, resp_to_l3
):
265 self
.reqToDir
= req_to_dir
266 self
.respToDir
= resp_to_dir
267 self
.l3UnblockToDir
= l3_unblock_to_dir
268 self
.reqToL3
= req_to_l3
269 self
.probeToL3
= probe_to_l3
270 self
.respToL3
= resp_to_l3
272 # Directory memory: Directory memory of infinite size which is
273 # used by directory controller to store the "states" of the
274 # state machine. The state machine is implemented per cache block
275 class DirMem(RubyDirectoryMemory
, CntrlBase
):
276 def create(self
, options
, ruby_system
, system
):
277 self
.version
= self
.versionCount()
278 phys_mem_size
= AddrRange(options
.mem_size
).size()
279 mem_module_size
= phys_mem_size
/ options
.num_dirs
280 dir_size
= MemorySize('0B')
281 dir_size
.value
= mem_module_size
284 # Directory controller: Contains directory memory, L3 cache and associated state
285 # machine which is used to accurately redirect a data request to L3 cache or to
286 # memory. The permissions requests do not come to this directory for region
287 # based protocols as they are handled exclusively by the region directory.
288 # However, region directory controller uses this directory controller for
289 # sending probe requests and receiving probe responses.
290 class DirCntrl(Directory_Controller
, CntrlBase
):
291 def create(self
, options
, ruby_system
, system
):
292 self
.version
= self
.versionCount()
293 self
.response_latency
= 25
294 self
.response_latency_regionDir
= 1
295 self
.directory
= DirMem()
296 self
.directory
.create(options
, ruby_system
, system
)
297 self
.L3CacheMemory
= L3Cache()
298 self
.L3CacheMemory
.create(options
, ruby_system
, system
)
299 self
.l3_hit_latency
= \
300 max(self
.L3CacheMemory
.dataAccessLatency
,
301 self
.L3CacheMemory
.tagAccessLatency
)
303 self
.ruby_system
= ruby_system
304 if options
.recycle_latency
:
305 self
.recycle_latency
= options
.recycle_latency
307 def connectWireBuffers(self
, req_to_dir
, resp_to_dir
, l3_unblock_to_dir
,
308 req_to_l3
, probe_to_l3
, resp_to_l3
):
309 self
.reqToDir
= req_to_dir
310 self
.respToDir
= resp_to_dir
311 self
.l3UnblockToDir
= l3_unblock_to_dir
312 self
.reqToL3
= req_to_l3
313 self
.probeToL3
= probe_to_l3
314 self
.respToL3
= resp_to_l3
316 # Region directory : Stores region permissions
317 class RegionDir(RubyCache
):
319 def create(self
, options
, ruby_system
, system
):
320 self
.block_size
= "%dB" % (64 * options
.blocks_per_region
)
321 self
.size
= options
.region_dir_entries
* \
322 self
.block_size
* options
.num_compute_units
324 self
.tagArrayBanks
= 8
325 self
.tagAccessLatency
= options
.dir_tag_latency
326 self
.dataAccessLatency
= 1
327 self
.resourceStalls
= options
.no_resource_stalls
328 self
.start_index_bit
= 6 + int(math
.log(options
.blocks_per_region
, 2))
329 self
.replacement_policy
= TreePLRURP(num_leaves
= self
.assoc
)
330 # Region directory controller : Contains region directory and associated state
331 # machine for dealing with region coherence requests.
332 class RegionCntrl(RegionDir_Controller
, CntrlBase
):
333 def create(self
, options
, ruby_system
, system
):
334 self
.version
= self
.versionCount()
335 self
.cacheMemory
= RegionDir()
336 self
.cacheMemory
.create(options
, ruby_system
, system
)
337 self
.blocksPerRegion
= options
.blocks_per_region
338 self
.toDirLatency
= \
339 max(self
.cacheMemory
.dataAccessLatency
,
340 self
.cacheMemory
.tagAccessLatency
)
341 self
.ruby_system
= ruby_system
342 self
.always_migrate
= options
.always_migrate
343 self
.sym_migrate
= options
.symmetric_migrate
344 self
.asym_migrate
= options
.asymmetric_migrate
345 if self
.always_migrate
:
346 assert(not self
.asym_migrate
and not self
.sym_migrate
)
348 assert(not self
.always_migrate
and not self
.asym_migrate
)
349 if self
.asym_migrate
:
350 assert(not self
.always_migrate
and not self
.sym_migrate
)
351 if options
.recycle_latency
:
352 self
.recycle_latency
= options
.recycle_latency
354 # Region Buffer: A region directory cache which avoids some potential
355 # long latency lookup of region directory for getting region permissions
356 class RegionBuffer(RubyCache
):
360 dataAccessLatency
= 1
362 resourceStalls
= True
364 class RBCntrl(RegionBuffer_Controller
, CntrlBase
):
365 def create(self
, options
, ruby_system
, system
):
366 self
.version
= self
.versionCount()
367 self
.cacheMemory
= RegionBuffer()
368 self
.cacheMemory
.resourceStalls
= options
.no_tcc_resource_stalls
369 self
.cacheMemory
.dataArrayBanks
= 64
370 self
.cacheMemory
.tagArrayBanks
= 64
371 self
.blocksPerRegion
= options
.blocks_per_region
372 self
.cacheMemory
.block_size
= "%dB" % (64 * self
.blocksPerRegion
)
373 self
.cacheMemory
.start_index_bit
= \
374 6 + int(math
.log(self
.blocksPerRegion
, 2))
375 self
.cacheMemory
.size
= options
.region_buffer_entries
* \
376 self
.cacheMemory
.block_size
* options
.num_compute_units
377 self
.toDirLatency
= options
.gpu_to_dir_latency
378 self
.toRegionDirLatency
= options
.cpu_to_dir_latency
380 TCC_bits
= int(math
.log(options
.num_tccs
, 2))
381 self
.TCC_select_num_bits
= TCC_bits
382 self
.ruby_system
= ruby_system
384 if options
.recycle_latency
:
385 self
.recycle_latency
= options
.recycle_latency
386 self
.cacheMemory
.replacement_policy
= \
387 TreePLRURP(num_leaves
= self
.cacheMemory
.assoc
)
389 def define_options(parser
):
390 parser
.add_option("--num-subcaches", type="int", default
=4)
391 parser
.add_option("--l3-data-latency", type="int", default
=20)
392 parser
.add_option("--l3-tag-latency", type="int", default
=15)
393 parser
.add_option("--cpu-to-dir-latency", type="int", default
=120)
394 parser
.add_option("--gpu-to-dir-latency", type="int", default
=60)
395 parser
.add_option("--no-resource-stalls", action
="store_false",
397 parser
.add_option("--no-tcc-resource-stalls", action
="store_false",
399 parser
.add_option("--num-tbes", type="int", default
=32)
400 parser
.add_option("--l2-latency", type="int", default
=50) # load to use
401 parser
.add_option("--num-tccs", type="int", default
=1,
402 help="number of TCC banks in the GPU")
404 parser
.add_option("--sqc-size", type='string', default
='32kB',
405 help="SQC cache size")
406 parser
.add_option("--sqc-assoc", type='int', default
=8,
407 help="SQC cache assoc")
409 parser
.add_option("--WB_L1", action
="store_true",
410 default
=False, help="L2 Writeback Cache")
411 parser
.add_option("--WB_L2", action
="store_true",
412 default
=False, help="L2 Writeback Cache")
413 parser
.add_option("--TCP_latency",
414 type="int", default
=4, help="TCP latency")
415 parser
.add_option("--TCC_latency",
416 type="int", default
=16, help="TCC latency")
417 parser
.add_option("--tcc-size", type='string', default
='2MB',
418 help="agregate tcc size")
419 parser
.add_option("--tcc-assoc", type='int', default
=16,
421 parser
.add_option("--tcp-size", type='string', default
='16kB',
424 parser
.add_option("--dir-tag-latency", type="int", default
=4)
425 parser
.add_option("--dir-tag-banks", type="int", default
=4)
426 parser
.add_option("--blocks-per-region", type="int", default
=16)
427 parser
.add_option("--dir-entries", type="int", default
=8192)
429 # Region buffer is a cache of region directory. Hence region
430 # directory is inclusive with respect to region directory.
431 # However, region directory is non-inclusive with respect to
432 # the caches in the system
433 parser
.add_option("--region-dir-entries", type="int", default
=1024)
434 parser
.add_option("--region-buffer-entries", type="int", default
=512)
436 parser
.add_option("--always-migrate",
437 action
="store_true", default
=False)
438 parser
.add_option("--symmetric-migrate",
439 action
="store_true", default
=False)
440 parser
.add_option("--asymmetric-migrate",
441 action
="store_true", default
=False)
442 parser
.add_option("--use-L3-on-WT", action
="store_true", default
=False)
444 def create_system(options
, full_system
, system
, dma_devices
, bootmem
,
446 if buildEnv
['PROTOCOL'] != 'GPU_VIPER_Region':
447 panic("This script requires the GPU_VIPER_Region protocol to be built.")
452 # The ruby network creation expects the list of nodes in the system to be
453 # consistent with the NetDest list. Therefore the l1 controller nodes
454 # must be listed before the directory nodes and directory nodes before
459 # For an odd number of CPUs, still create the right number of controllers
460 TCC_bits
= int(math
.log(options
.num_tccs
, 2))
463 # Must create the individual controllers before the network to ensure the
464 # controller constructors are called before the network constructor
467 # For an odd number of CPUs, still create the right number of controllers
468 crossbar_bw
= 16 * options
.num_compute_units
#Assuming a 2GHz clock
469 cpuCluster
= Cluster(extBW
= (crossbar_bw
), intBW
=crossbar_bw
)
470 for i
in range((options
.num_cpus
+ 1) // 2):
473 cp_cntrl
.create(options
, ruby_system
, system
)
476 rb_cntrl
.create(options
, ruby_system
, system
)
477 rb_cntrl
.number_of_TBEs
= 256
478 rb_cntrl
.isOnCPU
= True
480 cp_cntrl
.regionBufferNum
= rb_cntrl
.version
482 exec("system.cp_cntrl%d = cp_cntrl" % i
)
483 exec("system.rb_cntrl%d = rb_cntrl" % i
)
485 # Add controllers and sequencers to the appropriate lists
487 cpu_sequencers
.extend([cp_cntrl
.sequencer
, cp_cntrl
.sequencer1
])
489 # Connect the CP controllers and the network
490 cp_cntrl
.requestFromCore
= MessageBuffer()
491 cp_cntrl
.requestFromCore
.master
= ruby_system
.network
.slave
493 cp_cntrl
.responseFromCore
= MessageBuffer()
494 cp_cntrl
.responseFromCore
.master
= ruby_system
.network
.slave
496 cp_cntrl
.unblockFromCore
= MessageBuffer()
497 cp_cntrl
.unblockFromCore
.master
= ruby_system
.network
.slave
499 cp_cntrl
.probeToCore
= MessageBuffer()
500 cp_cntrl
.probeToCore
.slave
= ruby_system
.network
.master
502 cp_cntrl
.responseToCore
= MessageBuffer()
503 cp_cntrl
.responseToCore
.slave
= ruby_system
.network
.master
505 cp_cntrl
.mandatoryQueue
= MessageBuffer()
506 cp_cntrl
.triggerQueue
= MessageBuffer(ordered
= True)
508 # Connect the RB controllers to the ruby network
509 rb_cntrl
.requestFromCore
= MessageBuffer(ordered
= True)
510 rb_cntrl
.requestFromCore
.slave
= ruby_system
.network
.master
512 rb_cntrl
.responseFromCore
= MessageBuffer()
513 rb_cntrl
.responseFromCore
.slave
= ruby_system
.network
.master
515 rb_cntrl
.requestToNetwork
= MessageBuffer()
516 rb_cntrl
.requestToNetwork
.master
= ruby_system
.network
.slave
518 rb_cntrl
.notifyFromRegionDir
= MessageBuffer()
519 rb_cntrl
.notifyFromRegionDir
.slave
= ruby_system
.network
.master
521 rb_cntrl
.probeFromRegionDir
= MessageBuffer()
522 rb_cntrl
.probeFromRegionDir
.slave
= ruby_system
.network
.master
524 rb_cntrl
.unblockFromDir
= MessageBuffer()
525 rb_cntrl
.unblockFromDir
.slave
= ruby_system
.network
.master
527 rb_cntrl
.responseToRegDir
= MessageBuffer()
528 rb_cntrl
.responseToRegDir
.master
= ruby_system
.network
.slave
530 rb_cntrl
.triggerQueue
= MessageBuffer(ordered
= True)
532 cpuCluster
.add(cp_cntrl
)
533 cpuCluster
.add(rb_cntrl
)
535 gpuCluster
= Cluster(extBW
= (crossbar_bw
), intBW
= crossbar_bw
)
536 for i
in range(options
.num_compute_units
):
538 tcp_cntrl
= TCPCntrl(TCC_select_num_bits
= TCC_bits
,
540 number_of_TBEs
= 2560)
541 # TBEs set to max outstanding requests
542 tcp_cntrl
.create(options
, ruby_system
, system
)
543 tcp_cntrl
.WB
= options
.WB_L1
544 tcp_cntrl
.disableL1
= False
546 exec("system.tcp_cntrl%d = tcp_cntrl" % i
)
548 # Add controllers and sequencers to the appropriate lists
550 cpu_sequencers
.append(tcp_cntrl
.coalescer
)
552 # Connect the CP (TCP) controllers to the ruby network
553 tcp_cntrl
.requestFromTCP
= MessageBuffer(ordered
= True)
554 tcp_cntrl
.requestFromTCP
.master
= ruby_system
.network
.slave
556 tcp_cntrl
.responseFromTCP
= MessageBuffer(ordered
= True)
557 tcp_cntrl
.responseFromTCP
.master
= ruby_system
.network
.slave
559 tcp_cntrl
.unblockFromCore
= MessageBuffer()
560 tcp_cntrl
.unblockFromCore
.master
= ruby_system
.network
.slave
562 tcp_cntrl
.probeToTCP
= MessageBuffer(ordered
= True)
563 tcp_cntrl
.probeToTCP
.slave
= ruby_system
.network
.master
565 tcp_cntrl
.responseToTCP
= MessageBuffer(ordered
= True)
566 tcp_cntrl
.responseToTCP
.slave
= ruby_system
.network
.master
568 tcp_cntrl
.mandatoryQueue
= MessageBuffer()
570 gpuCluster
.add(tcp_cntrl
)
572 for i
in range(options
.num_sqc
):
574 sqc_cntrl
= SQCCntrl(TCC_select_num_bits
= TCC_bits
)
575 sqc_cntrl
.create(options
, ruby_system
, system
)
577 exec("system.sqc_cntrl%d = sqc_cntrl" % i
)
579 # Add controllers and sequencers to the appropriate lists
581 cpu_sequencers
.append(sqc_cntrl
.sequencer
)
583 # Connect the SQC controller to the ruby network
584 sqc_cntrl
.requestFromSQC
= MessageBuffer(ordered
= True)
585 sqc_cntrl
.requestFromSQC
.master
= ruby_system
.network
.slave
587 sqc_cntrl
.probeToSQC
= MessageBuffer(ordered
= True)
588 sqc_cntrl
.probeToSQC
.slave
= ruby_system
.network
.master
590 sqc_cntrl
.responseToSQC
= MessageBuffer(ordered
= True)
591 sqc_cntrl
.responseToSQC
.slave
= ruby_system
.network
.master
593 sqc_cntrl
.mandatoryQueue
= MessageBuffer()
595 # SQC also in GPU cluster
596 gpuCluster
.add(sqc_cntrl
)
600 for i
in range(options
.num_tccs
):
602 tcc_cntrl
= TCCCntrl()
603 tcc_cntrl
.create(options
, ruby_system
, system
)
604 tcc_cntrl
.l2_request_latency
= 1
605 tcc_cntrl
.l2_response_latency
= options
.TCC_latency
606 tcc_cntrl
.WB
= options
.WB_L2
607 tcc_cntrl
.number_of_TBEs
= 2560 * options
.num_compute_units
609 # Connect the TCC controllers to the ruby network
610 tcc_cntrl
.requestFromTCP
= MessageBuffer(ordered
= True)
611 tcc_cntrl
.requestFromTCP
.slave
= ruby_system
.network
.master
613 tcc_cntrl
.responseToCore
= MessageBuffer(ordered
= True)
614 tcc_cntrl
.responseToCore
.master
= ruby_system
.network
.slave
616 tcc_cntrl
.probeFromNB
= MessageBuffer()
617 tcc_cntrl
.probeFromNB
.slave
= ruby_system
.network
.master
619 tcc_cntrl
.responseFromNB
= MessageBuffer()
620 tcc_cntrl
.responseFromNB
.slave
= ruby_system
.network
.master
622 tcc_cntrl
.requestToNB
= MessageBuffer(ordered
= True)
623 tcc_cntrl
.requestToNB
.master
= ruby_system
.network
.slave
625 tcc_cntrl
.responseToNB
= MessageBuffer()
626 tcc_cntrl
.responseToNB
.master
= ruby_system
.network
.slave
628 tcc_cntrl
.unblockToNB
= MessageBuffer()
629 tcc_cntrl
.unblockToNB
.master
= ruby_system
.network
.slave
631 tcc_cntrl
.triggerQueue
= MessageBuffer(ordered
= True)
634 rb_cntrl
.create(options
, ruby_system
, system
)
635 rb_cntrl
.number_of_TBEs
= 2560 * options
.num_compute_units
636 rb_cntrl
.isOnCPU
= False
638 # Connect the RB controllers to the ruby network
639 rb_cntrl
.requestFromCore
= MessageBuffer(ordered
= True)
640 rb_cntrl
.requestFromCore
.slave
= ruby_system
.network
.master
642 rb_cntrl
.responseFromCore
= MessageBuffer()
643 rb_cntrl
.responseFromCore
.slave
= ruby_system
.network
.master
645 rb_cntrl
.requestToNetwork
= MessageBuffer()
646 rb_cntrl
.requestToNetwork
.master
= ruby_system
.network
.slave
648 rb_cntrl
.notifyFromRegionDir
= MessageBuffer()
649 rb_cntrl
.notifyFromRegionDir
.slave
= ruby_system
.network
.master
651 rb_cntrl
.probeFromRegionDir
= MessageBuffer()
652 rb_cntrl
.probeFromRegionDir
.slave
= ruby_system
.network
.master
654 rb_cntrl
.unblockFromDir
= MessageBuffer()
655 rb_cntrl
.unblockFromDir
.slave
= ruby_system
.network
.master
657 rb_cntrl
.responseToRegDir
= MessageBuffer()
658 rb_cntrl
.responseToRegDir
.master
= ruby_system
.network
.slave
660 rb_cntrl
.triggerQueue
= MessageBuffer(ordered
= True)
662 tcc_cntrl
.regionBufferNum
= rb_cntrl
.version
664 exec("system.tcc_cntrl%d = tcc_cntrl" % i
)
665 exec("system.tcc_rb_cntrl%d = rb_cntrl" % i
)
667 # TCC cntrls added to the GPU cluster
668 gpuCluster
.add(tcc_cntrl
)
669 gpuCluster
.add(rb_cntrl
)
671 # Because of wire buffers, num_l3caches must equal num_dirs
672 # Region coherence only works with 1 dir
673 assert(options
.num_l3caches
== options
.num_dirs
== 1)
675 # This is the base crossbar that connects the L3s, Dirs, and cpu/gpu
677 mainCluster
= Cluster(intBW
= crossbar_bw
)
679 dir_cntrl
= DirCntrl()
680 dir_cntrl
.create(options
, ruby_system
, system
)
681 dir_cntrl
.number_of_TBEs
= 2560 * options
.num_compute_units
682 dir_cntrl
.useL3OnWT
= options
.use_L3_on_WT
684 # Connect the Directory controller to the ruby network
685 dir_cntrl
.requestFromCores
= MessageBuffer()
686 dir_cntrl
.requestFromCores
.slave
= ruby_system
.network
.master
688 dir_cntrl
.responseFromCores
= MessageBuffer()
689 dir_cntrl
.responseFromCores
.slave
= ruby_system
.network
.master
691 dir_cntrl
.unblockFromCores
= MessageBuffer()
692 dir_cntrl
.unblockFromCores
.slave
= ruby_system
.network
.master
694 dir_cntrl
.probeToCore
= MessageBuffer()
695 dir_cntrl
.probeToCore
.master
= ruby_system
.network
.slave
697 dir_cntrl
.responseToCore
= MessageBuffer()
698 dir_cntrl
.responseToCore
.master
= ruby_system
.network
.slave
700 dir_cntrl
.reqFromRegBuf
= MessageBuffer()
701 dir_cntrl
.reqFromRegBuf
.slave
= ruby_system
.network
.master
703 dir_cntrl
.reqToRegDir
= MessageBuffer(ordered
= True)
704 dir_cntrl
.reqToRegDir
.master
= ruby_system
.network
.slave
706 dir_cntrl
.reqFromRegDir
= MessageBuffer(ordered
= True)
707 dir_cntrl
.reqFromRegDir
.slave
= ruby_system
.network
.master
709 dir_cntrl
.unblockToRegDir
= MessageBuffer()
710 dir_cntrl
.unblockToRegDir
.master
= ruby_system
.network
.slave
712 dir_cntrl
.triggerQueue
= MessageBuffer(ordered
= True)
713 dir_cntrl
.L3triggerQueue
= MessageBuffer(ordered
= True)
714 dir_cntrl
.responseFromMemory
= MessageBuffer()
716 exec("system.dir_cntrl%d = dir_cntrl" % i
)
717 dir_cntrl_nodes
.append(dir_cntrl
)
719 mainCluster
.add(dir_cntrl
)
721 reg_cntrl
= RegionCntrl(noTCCdir
=True,TCC_select_num_bits
= TCC_bits
)
722 reg_cntrl
.create(options
, ruby_system
, system
)
723 reg_cntrl
.number_of_TBEs
= options
.num_tbes
724 reg_cntrl
.cpuRegionBufferNum
= system
.rb_cntrl0
.version
725 reg_cntrl
.gpuRegionBufferNum
= system
.tcc_rb_cntrl0
.version
727 # Connect the Region Dir controllers to the ruby network
728 reg_cntrl
.requestToDir
= MessageBuffer(ordered
= True)
729 reg_cntrl
.requestToDir
.master
= ruby_system
.network
.slave
731 reg_cntrl
.notifyToRBuffer
= MessageBuffer()
732 reg_cntrl
.notifyToRBuffer
.master
= ruby_system
.network
.slave
734 reg_cntrl
.probeToRBuffer
= MessageBuffer()
735 reg_cntrl
.probeToRBuffer
.master
= ruby_system
.network
.slave
737 reg_cntrl
.responseFromRBuffer
= MessageBuffer()
738 reg_cntrl
.responseFromRBuffer
.slave
= ruby_system
.network
.master
740 reg_cntrl
.requestFromRegBuf
= MessageBuffer()
741 reg_cntrl
.requestFromRegBuf
.slave
= ruby_system
.network
.master
743 reg_cntrl
.triggerQueue
= MessageBuffer(ordered
= True)
745 exec("system.reg_cntrl%d = reg_cntrl" % i
)
747 mainCluster
.add(reg_cntrl
)
749 # Assuming no DMA devices
750 assert(len(dma_devices
) == 0)
752 # Add cpu/gpu clusters to main cluster
753 mainCluster
.add(cpuCluster
)
754 mainCluster
.add(gpuCluster
)
756 ruby_system
.network
.number_of_virtual_networks
= 10
758 return (cpu_sequencers
, dir_cntrl_nodes
, mainCluster
)