configs: Replace DirMem w/RubyDirectoryMemory, set addr_ranges
[gem5.git] / configs / ruby / GPU_VIPER_Region.py
1 # Copyright (c) 2015 Advanced Micro Devices, Inc.
2 # All rights reserved.
3 #
4 # For use for simulation and test purposes only
5 #
6 # Redistribution and use in source and binary forms, with or without
7 # modification, are permitted provided that the following conditions are met:
8 #
9 # 1. Redistributions of source code must retain the above copyright notice,
10 # this list of conditions and the following disclaimer.
11 #
12 # 2. Redistributions in binary form must reproduce the above copyright notice,
13 # this list of conditions and the following disclaimer in the documentation
14 # and/or other materials provided with the distribution.
15 #
16 # 3. Neither the name of the copyright holder nor the names of its
17 # contributors may be used to endorse or promote products derived from this
18 # software without specific prior written permission.
19 #
20 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
24 # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 # POSSIBILITY OF SUCH DAMAGE.
31
32 import six
33 import math
34 import m5
35 from m5.objects import *
36 from m5.defines import buildEnv
37 from m5.util import addToPath
38 from .Ruby import send_evicts
39
40 addToPath('../')
41
42 from topologies.Cluster import Cluster
43
44 if six.PY3:
45 long = int
46
47 class CntrlBase:
48 _seqs = 0
49 @classmethod
50 def seqCount(cls):
51 # Use SeqCount not class since we need global count
52 CntrlBase._seqs += 1
53 return CntrlBase._seqs - 1
54
55 _cntrls = 0
56 @classmethod
57 def cntrlCount(cls):
58 # Use CntlCount not class since we need global count
59 CntrlBase._cntrls += 1
60 return CntrlBase._cntrls - 1
61
62 _version = 0
63 @classmethod
64 def versionCount(cls):
65 cls._version += 1 # Use count for this particular type
66 return cls._version - 1
67
68 #
69 # Note: the L1 Cache latency is only used by the sequencer on fast path hits
70 #
71 class L1Cache(RubyCache):
72 resourceStalls = False
73 dataArrayBanks = 2
74 tagArrayBanks = 2
75 dataAccessLatency = 1
76 tagAccessLatency = 1
77 def create(self, size, assoc, options):
78 self.size = MemorySize(size)
79 self.assoc = assoc
80 self.replacement_policy = TreePLRURP()
81
82 class L2Cache(RubyCache):
83 resourceStalls = False
84 assoc = 16
85 dataArrayBanks = 16
86 tagArrayBanks = 16
87 def create(self, size, assoc, options):
88 self.size = MemorySize(size)
89 self.assoc = assoc
90 self.replacement_policy = TreePLRURP()
91
92 class CPCntrl(CorePair_Controller, CntrlBase):
93
94 def create(self, options, ruby_system, system):
95 self.version = self.versionCount()
96
97 self.L1Icache = L1Cache()
98 self.L1Icache.create(options.l1i_size, options.l1i_assoc, options)
99 self.L1D0cache = L1Cache()
100 self.L1D0cache.create(options.l1d_size, options.l1d_assoc, options)
101 self.L1D1cache = L1Cache()
102 self.L1D1cache.create(options.l1d_size, options.l1d_assoc, options)
103 self.L2cache = L2Cache()
104 self.L2cache.create(options.l2_size, options.l2_assoc, options)
105
106 self.sequencer = RubySequencer()
107 self.sequencer.version = self.seqCount()
108 self.sequencer.icache = self.L1Icache
109 self.sequencer.dcache = self.L1D0cache
110 self.sequencer.ruby_system = ruby_system
111 self.sequencer.coreid = 0
112 self.sequencer.is_cpu_sequencer = True
113
114 self.sequencer1 = RubySequencer()
115 self.sequencer1.version = self.seqCount()
116 self.sequencer1.icache = self.L1Icache
117 self.sequencer1.dcache = self.L1D1cache
118 self.sequencer1.ruby_system = ruby_system
119 self.sequencer1.coreid = 1
120 self.sequencer1.is_cpu_sequencer = True
121
122 self.issue_latency = 1
123 self.send_evictions = send_evicts(options)
124
125 self.ruby_system = ruby_system
126
127 if options.recycle_latency:
128 self.recycle_latency = options.recycle_latency
129
130 class TCPCache(RubyCache):
131 size = "16kB"
132 assoc = 16
133 dataArrayBanks = 16
134 tagArrayBanks = 16
135 dataAccessLatency = 4
136 tagAccessLatency = 1
137 def create(self, options):
138 self.size = MemorySize(options.tcp_size)
139 self.dataArrayBanks = 16
140 self.tagArrayBanks = 16
141 self.dataAccessLatency = 4
142 self.tagAccessLatency = 1
143 self.resourceStalls = options.no_tcc_resource_stalls
144 self.replacement_policy = TreePLRURP(num_leaves = self.assoc)
145
146 class TCPCntrl(TCP_Controller, CntrlBase):
147
148 def create(self, options, ruby_system, system):
149 self.version = self.versionCount()
150 self.L1cache = TCPCache(dataAccessLatency = options.TCP_latency)
151 self.L1cache.create(options)
152 self.issue_latency = 1
153
154 self.coalescer = VIPERCoalescer()
155 self.coalescer.version = self.seqCount()
156 self.coalescer.icache = self.L1cache
157 self.coalescer.dcache = self.L1cache
158 self.coalescer.ruby_system = ruby_system
159 self.coalescer.support_inst_reqs = False
160 self.coalescer.is_cpu_sequencer = False
161 if options.tcp_deadlock_threshold:
162 self.coalescer.deadlock_threshold = \
163 options.tcp_deadlock_threshold
164 self.coalescer.max_coalesces_per_cycle = \
165 options.max_coalesces_per_cycle
166
167 self.sequencer = RubySequencer()
168 self.sequencer.version = self.seqCount()
169 self.sequencer.icache = self.L1cache
170 self.sequencer.dcache = self.L1cache
171 self.sequencer.ruby_system = ruby_system
172 self.sequencer.is_cpu_sequencer = True
173
174 self.use_seq_not_coal = False
175
176 self.ruby_system = ruby_system
177 if options.recycle_latency:
178 self.recycle_latency = options.recycle_latency
179
180 class SQCCache(RubyCache):
181 dataArrayBanks = 8
182 tagArrayBanks = 8
183 dataAccessLatency = 1
184 tagAccessLatency = 1
185
186 def create(self, options):
187 self.size = MemorySize(options.sqc_size)
188 self.assoc = options.sqc_assoc
189 self.replacement_policy = TreePLRURP(num_leaves = self.assoc)
190
191 class SQCCntrl(SQC_Controller, CntrlBase):
192
193 def create(self, options, ruby_system, system):
194 self.version = self.versionCount()
195 self.L1cache = SQCCache()
196 self.L1cache.create(options)
197 self.L1cache.resourceStalls = False
198 self.sequencer = RubySequencer()
199 self.sequencer.version = self.seqCount()
200 self.sequencer.icache = self.L1cache
201 self.sequencer.dcache = self.L1cache
202 self.sequencer.ruby_system = ruby_system
203 self.sequencer.support_data_reqs = False
204 self.sequencer.is_cpu_sequencer = False
205 if options.sqc_deadlock_threshold:
206 self.sequencer.deadlock_threshold = \
207 options.sqc_deadlock_threshold
208
209 self.ruby_system = ruby_system
210 if options.recycle_latency:
211 self.recycle_latency = options.recycle_latency
212
213 class TCC(RubyCache):
214 size = MemorySize("256kB")
215 assoc = 16
216 dataAccessLatency = 8
217 tagAccessLatency = 2
218 resourceStalls = False
219 def create(self, options):
220 self.assoc = options.tcc_assoc
221 if hasattr(options, 'bw_scalor') and options.bw_scalor > 0:
222 s = options.num_compute_units
223 tcc_size = s * 128
224 tcc_size = str(tcc_size)+'kB'
225 self.size = MemorySize(tcc_size)
226 self.dataArrayBanks = 64
227 self.tagArrayBanks = 64
228 else:
229 self.size = MemorySize(options.tcc_size)
230 self.dataArrayBanks = 256 / options.num_tccs #number of data banks
231 self.tagArrayBanks = 256 / options.num_tccs #number of tag banks
232 self.size.value = self.size.value / options.num_tccs
233 if ((self.size.value / long(self.assoc)) < 128):
234 self.size.value = long(128 * self.assoc)
235 self.start_index_bit = math.log(options.cacheline_size, 2) + \
236 math.log(options.num_tccs, 2)
237 self.replacement_policy = TreePLRURP(num_leaves = self.assoc)
238
239 class TCCCntrl(TCC_Controller, CntrlBase):
240 def create(self, options, ruby_system, system):
241 self.version = self.versionCount()
242 self.L2cache = TCC()
243 self.L2cache.create(options)
244 self.ruby_system = ruby_system
245 if options.recycle_latency:
246 self.recycle_latency = options.recycle_latency
247
248 class L3Cache(RubyCache):
249 dataArrayBanks = 16
250 tagArrayBanks = 16
251
252 def create(self, options, ruby_system, system):
253 self.size = MemorySize(options.l3_size)
254 self.size.value /= options.num_dirs
255 self.assoc = options.l3_assoc
256 self.dataArrayBanks /= options.num_dirs
257 self.tagArrayBanks /= options.num_dirs
258 self.dataArrayBanks /= options.num_dirs
259 self.tagArrayBanks /= options.num_dirs
260 self.dataAccessLatency = options.l3_data_latency
261 self.tagAccessLatency = options.l3_tag_latency
262 self.resourceStalls = False
263 self.replacement_policy = TreePLRURP(num_leaves = self.assoc)
264
265 class L3Cntrl(L3Cache_Controller, CntrlBase):
266 def create(self, options, ruby_system, system):
267 self.version = self.versionCount()
268 self.L3cache = L3Cache()
269 self.L3cache.create(options, ruby_system, system)
270 self.l3_response_latency = \
271 max(self.L3cache.dataAccessLatency, self.L3cache.tagAccessLatency)
272 self.ruby_system = ruby_system
273 if options.recycle_latency:
274 self.recycle_latency = options.recycle_latency
275
276 def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir,
277 req_to_l3, probe_to_l3, resp_to_l3):
278 self.reqToDir = req_to_dir
279 self.respToDir = resp_to_dir
280 self.l3UnblockToDir = l3_unblock_to_dir
281 self.reqToL3 = req_to_l3
282 self.probeToL3 = probe_to_l3
283 self.respToL3 = resp_to_l3
284
285 # Directory controller: Contains directory memory, L3 cache and associated
286 # state machine which is used to accurately redirect a data request to L3 cache
287 # or memory. The permissions requests do not come to this directory for region
288 # based protocols as they are handled exclusively by the region directory.
289 # However, region directory controller uses this directory controller for
290 # sending probe requests and receiving probe responses.
291 class DirCntrl(Directory_Controller, CntrlBase):
292 def create(self, options, dir_ranges, ruby_system, system):
293 self.version = self.versionCount()
294 self.response_latency = 25
295 self.response_latency_regionDir = 1
296 self.addr_ranges = dir_ranges
297 self.directory = RubyDirectoryMemory()
298 self.L3CacheMemory = L3Cache()
299 self.L3CacheMemory.create(options, ruby_system, system)
300 self.l3_hit_latency = \
301 max(self.L3CacheMemory.dataAccessLatency,
302 self.L3CacheMemory.tagAccessLatency)
303
304 self.ruby_system = ruby_system
305 if options.recycle_latency:
306 self.recycle_latency = options.recycle_latency
307
308 def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir,
309 req_to_l3, probe_to_l3, resp_to_l3):
310 self.reqToDir = req_to_dir
311 self.respToDir = resp_to_dir
312 self.l3UnblockToDir = l3_unblock_to_dir
313 self.reqToL3 = req_to_l3
314 self.probeToL3 = probe_to_l3
315 self.respToL3 = resp_to_l3
316
317 # Region directory : Stores region permissions
318 class RegionDir(RubyCache):
319
320 def create(self, options, ruby_system, system):
321 self.block_size = "%dB" % (64 * options.blocks_per_region)
322 self.size = options.region_dir_entries * \
323 self.block_size * options.num_compute_units
324 self.assoc = 8
325 self.tagArrayBanks = 8
326 self.tagAccessLatency = options.dir_tag_latency
327 self.dataAccessLatency = 1
328 self.resourceStalls = options.no_resource_stalls
329 self.start_index_bit = 6 + int(math.log(options.blocks_per_region, 2))
330 self.replacement_policy = TreePLRURP(num_leaves = self.assoc)
331 # Region directory controller : Contains region directory and associated state
332 # machine for dealing with region coherence requests.
333 class RegionCntrl(RegionDir_Controller, CntrlBase):
334 def create(self, options, ruby_system, system):
335 self.version = self.versionCount()
336 self.cacheMemory = RegionDir()
337 self.cacheMemory.create(options, ruby_system, system)
338 self.blocksPerRegion = options.blocks_per_region
339 self.toDirLatency = \
340 max(self.cacheMemory.dataAccessLatency,
341 self.cacheMemory.tagAccessLatency)
342 self.ruby_system = ruby_system
343 self.always_migrate = options.always_migrate
344 self.sym_migrate = options.symmetric_migrate
345 self.asym_migrate = options.asymmetric_migrate
346 if self.always_migrate:
347 assert(not self.asym_migrate and not self.sym_migrate)
348 if self.sym_migrate:
349 assert(not self.always_migrate and not self.asym_migrate)
350 if self.asym_migrate:
351 assert(not self.always_migrate and not self.sym_migrate)
352 if options.recycle_latency:
353 self.recycle_latency = options.recycle_latency
354
355 # Region Buffer: A region directory cache which avoids some potential
356 # long latency lookup of region directory for getting region permissions
357 class RegionBuffer(RubyCache):
358 assoc = 4
359 dataArrayBanks = 256
360 tagArrayBanks = 256
361 dataAccessLatency = 1
362 tagAccessLatency = 1
363 resourceStalls = True
364
365 class RBCntrl(RegionBuffer_Controller, CntrlBase):
366 def create(self, options, ruby_system, system):
367 self.version = self.versionCount()
368 self.cacheMemory = RegionBuffer()
369 self.cacheMemory.resourceStalls = options.no_tcc_resource_stalls
370 self.cacheMemory.dataArrayBanks = 64
371 self.cacheMemory.tagArrayBanks = 64
372 self.blocksPerRegion = options.blocks_per_region
373 self.cacheMemory.block_size = "%dB" % (64 * self.blocksPerRegion)
374 self.cacheMemory.start_index_bit = \
375 6 + int(math.log(self.blocksPerRegion, 2))
376 self.cacheMemory.size = options.region_buffer_entries * \
377 self.cacheMemory.block_size * options.num_compute_units
378 self.toDirLatency = options.gpu_to_dir_latency
379 self.toRegionDirLatency = options.cpu_to_dir_latency
380 self.noTCCdir = True
381 TCC_bits = int(math.log(options.num_tccs, 2))
382 self.TCC_select_num_bits = TCC_bits
383 self.ruby_system = ruby_system
384
385 if options.recycle_latency:
386 self.recycle_latency = options.recycle_latency
387 self.cacheMemory.replacement_policy = \
388 TreePLRURP(num_leaves = self.cacheMemory.assoc)
389
390 def define_options(parser):
391 parser.add_option("--num-subcaches", type="int", default=4)
392 parser.add_option("--l3-data-latency", type="int", default=20)
393 parser.add_option("--l3-tag-latency", type="int", default=15)
394 parser.add_option("--cpu-to-dir-latency", type="int", default=120)
395 parser.add_option("--gpu-to-dir-latency", type="int", default=60)
396 parser.add_option("--no-resource-stalls", action="store_false",
397 default=True)
398 parser.add_option("--no-tcc-resource-stalls", action="store_false",
399 default=True)
400 parser.add_option("--num-tbes", type="int", default=32)
401 parser.add_option("--l2-latency", type="int", default=50) # load to use
402 parser.add_option("--num-tccs", type="int", default=1,
403 help="number of TCC banks in the GPU")
404
405 parser.add_option("--sqc-size", type='string', default='32kB',
406 help="SQC cache size")
407 parser.add_option("--sqc-assoc", type='int', default=8,
408 help="SQC cache assoc")
409 parser.add_option("--sqc-deadlock-threshold", type='int',
410 help="Set the SQC deadlock threshold to some value")
411
412 parser.add_option("--WB_L1", action="store_true",
413 default=False, help="L2 Writeback Cache")
414 parser.add_option("--WB_L2", action="store_true",
415 default=False, help="L2 Writeback Cache")
416 parser.add_option("--TCP_latency",
417 type="int", default=4, help="TCP latency")
418 parser.add_option("--TCC_latency",
419 type="int", default=16, help="TCC latency")
420 parser.add_option("--tcc-size", type='string', default='2MB',
421 help="agregate tcc size")
422 parser.add_option("--tcc-assoc", type='int', default=16,
423 help="tcc assoc")
424 parser.add_option("--tcp-size", type='string', default='16kB',
425 help="tcp size")
426 parser.add_option("--tcp-deadlock-threshold", type='int',
427 help="Set the TCP deadlock threshold to some value")
428 parser.add_option("--max-coalesces-per-cycle", type="int", default=1,
429 help="Maximum insts that may coalesce in a cycle");
430
431 parser.add_option("--dir-tag-latency", type="int", default=4)
432 parser.add_option("--dir-tag-banks", type="int", default=4)
433 parser.add_option("--blocks-per-region", type="int", default=16)
434 parser.add_option("--dir-entries", type="int", default=8192)
435
436 # Region buffer is a cache of region directory. Hence region
437 # directory is inclusive with respect to region directory.
438 # However, region directory is non-inclusive with respect to
439 # the caches in the system
440 parser.add_option("--region-dir-entries", type="int", default=1024)
441 parser.add_option("--region-buffer-entries", type="int", default=512)
442
443 parser.add_option("--always-migrate",
444 action="store_true", default=False)
445 parser.add_option("--symmetric-migrate",
446 action="store_true", default=False)
447 parser.add_option("--asymmetric-migrate",
448 action="store_true", default=False)
449 parser.add_option("--use-L3-on-WT", action="store_true", default=False)
450
451 def create_system(options, full_system, system, dma_devices, bootmem,
452 ruby_system):
453 if buildEnv['PROTOCOL'] != 'GPU_VIPER_Region':
454 panic("This script requires the GPU_VIPER_Region protocol to be built.")
455
456 cpu_sequencers = []
457
458 #
459 # The ruby network creation expects the list of nodes in the system to be
460 # consistent with the NetDest list. Therefore the l1 controller nodes
461 # must be listed before the directory nodes and directory nodes before
462 # dma nodes, etc.
463 #
464 dir_cntrl_nodes = []
465
466 # For an odd number of CPUs, still create the right number of controllers
467 TCC_bits = int(math.log(options.num_tccs, 2))
468
469 #
470 # Must create the individual controllers before the network to ensure the
471 # controller constructors are called before the network constructor
472 #
473
474 # For an odd number of CPUs, still create the right number of controllers
475 crossbar_bw = 16 * options.num_compute_units #Assuming a 2GHz clock
476 cpuCluster = Cluster(extBW = (crossbar_bw), intBW=crossbar_bw)
477 for i in range((options.num_cpus + 1) // 2):
478
479 cp_cntrl = CPCntrl()
480 cp_cntrl.create(options, ruby_system, system)
481
482 rb_cntrl = RBCntrl()
483 rb_cntrl.create(options, ruby_system, system)
484 rb_cntrl.number_of_TBEs = 256
485 rb_cntrl.isOnCPU = True
486
487 cp_cntrl.regionBufferNum = rb_cntrl.version
488
489 exec("system.cp_cntrl%d = cp_cntrl" % i)
490 exec("system.rb_cntrl%d = rb_cntrl" % i)
491 #
492 # Add controllers and sequencers to the appropriate lists
493 #
494 cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1])
495
496 # Connect the CP controllers and the network
497 cp_cntrl.requestFromCore = MessageBuffer()
498 cp_cntrl.requestFromCore.master = ruby_system.network.slave
499
500 cp_cntrl.responseFromCore = MessageBuffer()
501 cp_cntrl.responseFromCore.master = ruby_system.network.slave
502
503 cp_cntrl.unblockFromCore = MessageBuffer()
504 cp_cntrl.unblockFromCore.master = ruby_system.network.slave
505
506 cp_cntrl.probeToCore = MessageBuffer()
507 cp_cntrl.probeToCore.slave = ruby_system.network.master
508
509 cp_cntrl.responseToCore = MessageBuffer()
510 cp_cntrl.responseToCore.slave = ruby_system.network.master
511
512 cp_cntrl.mandatoryQueue = MessageBuffer()
513 cp_cntrl.triggerQueue = MessageBuffer(ordered = True)
514
515 # Connect the RB controllers to the ruby network
516 rb_cntrl.requestFromCore = MessageBuffer(ordered = True)
517 rb_cntrl.requestFromCore.slave = ruby_system.network.master
518
519 rb_cntrl.responseFromCore = MessageBuffer()
520 rb_cntrl.responseFromCore.slave = ruby_system.network.master
521
522 rb_cntrl.requestToNetwork = MessageBuffer()
523 rb_cntrl.requestToNetwork.master = ruby_system.network.slave
524
525 rb_cntrl.notifyFromRegionDir = MessageBuffer()
526 rb_cntrl.notifyFromRegionDir.slave = ruby_system.network.master
527
528 rb_cntrl.probeFromRegionDir = MessageBuffer()
529 rb_cntrl.probeFromRegionDir.slave = ruby_system.network.master
530
531 rb_cntrl.unblockFromDir = MessageBuffer()
532 rb_cntrl.unblockFromDir.slave = ruby_system.network.master
533
534 rb_cntrl.responseToRegDir = MessageBuffer()
535 rb_cntrl.responseToRegDir.master = ruby_system.network.slave
536
537 rb_cntrl.triggerQueue = MessageBuffer(ordered = True)
538
539 cpuCluster.add(cp_cntrl)
540 cpuCluster.add(rb_cntrl)
541
542 gpuCluster = Cluster(extBW = (crossbar_bw), intBW = crossbar_bw)
543 for i in range(options.num_compute_units):
544
545 tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits,
546 issue_latency = 1,
547 number_of_TBEs = 2560)
548 # TBEs set to max outstanding requests
549 tcp_cntrl.create(options, ruby_system, system)
550 tcp_cntrl.WB = options.WB_L1
551 tcp_cntrl.disableL1 = False
552
553 exec("system.tcp_cntrl%d = tcp_cntrl" % i)
554 #
555 # Add controllers and sequencers to the appropriate lists
556 #
557 cpu_sequencers.append(tcp_cntrl.coalescer)
558
559 # Connect the CP (TCP) controllers to the ruby network
560 tcp_cntrl.requestFromTCP = MessageBuffer(ordered = True)
561 tcp_cntrl.requestFromTCP.master = ruby_system.network.slave
562
563 tcp_cntrl.responseFromTCP = MessageBuffer(ordered = True)
564 tcp_cntrl.responseFromTCP.master = ruby_system.network.slave
565
566 tcp_cntrl.unblockFromCore = MessageBuffer()
567 tcp_cntrl.unblockFromCore.master = ruby_system.network.slave
568
569 tcp_cntrl.probeToTCP = MessageBuffer(ordered = True)
570 tcp_cntrl.probeToTCP.slave = ruby_system.network.master
571
572 tcp_cntrl.responseToTCP = MessageBuffer(ordered = True)
573 tcp_cntrl.responseToTCP.slave = ruby_system.network.master
574
575 tcp_cntrl.mandatoryQueue = MessageBuffer()
576
577 gpuCluster.add(tcp_cntrl)
578
579 for i in range(options.num_sqc):
580
581 sqc_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits)
582 sqc_cntrl.create(options, ruby_system, system)
583
584 exec("system.sqc_cntrl%d = sqc_cntrl" % i)
585 #
586 # Add controllers and sequencers to the appropriate lists
587 #
588 cpu_sequencers.append(sqc_cntrl.sequencer)
589
590 # Connect the SQC controller to the ruby network
591 sqc_cntrl.requestFromSQC = MessageBuffer(ordered = True)
592 sqc_cntrl.requestFromSQC.master = ruby_system.network.slave
593
594 sqc_cntrl.probeToSQC = MessageBuffer(ordered = True)
595 sqc_cntrl.probeToSQC.slave = ruby_system.network.master
596
597 sqc_cntrl.responseToSQC = MessageBuffer(ordered = True)
598 sqc_cntrl.responseToSQC.slave = ruby_system.network.master
599
600 sqc_cntrl.mandatoryQueue = MessageBuffer()
601
602 # SQC also in GPU cluster
603 gpuCluster.add(sqc_cntrl)
604
605 numa_bit = 6
606
607 for i in range(options.num_tccs):
608
609 tcc_cntrl = TCCCntrl()
610 tcc_cntrl.create(options, ruby_system, system)
611 tcc_cntrl.l2_request_latency = 1
612 tcc_cntrl.l2_response_latency = options.TCC_latency
613 tcc_cntrl.WB = options.WB_L2
614 tcc_cntrl.number_of_TBEs = 2560 * options.num_compute_units
615
616 # Connect the TCC controllers to the ruby network
617 tcc_cntrl.requestFromTCP = MessageBuffer(ordered = True)
618 tcc_cntrl.requestFromTCP.slave = ruby_system.network.master
619
620 tcc_cntrl.responseToCore = MessageBuffer(ordered = True)
621 tcc_cntrl.responseToCore.master = ruby_system.network.slave
622
623 tcc_cntrl.probeFromNB = MessageBuffer()
624 tcc_cntrl.probeFromNB.slave = ruby_system.network.master
625
626 tcc_cntrl.responseFromNB = MessageBuffer()
627 tcc_cntrl.responseFromNB.slave = ruby_system.network.master
628
629 tcc_cntrl.requestToNB = MessageBuffer(ordered = True)
630 tcc_cntrl.requestToNB.master = ruby_system.network.slave
631
632 tcc_cntrl.responseToNB = MessageBuffer()
633 tcc_cntrl.responseToNB.master = ruby_system.network.slave
634
635 tcc_cntrl.unblockToNB = MessageBuffer()
636 tcc_cntrl.unblockToNB.master = ruby_system.network.slave
637
638 tcc_cntrl.triggerQueue = MessageBuffer(ordered = True)
639
640 rb_cntrl = RBCntrl()
641 rb_cntrl.create(options, ruby_system, system)
642 rb_cntrl.number_of_TBEs = 2560 * options.num_compute_units
643 rb_cntrl.isOnCPU = False
644
645 # Connect the RB controllers to the ruby network
646 rb_cntrl.requestFromCore = MessageBuffer(ordered = True)
647 rb_cntrl.requestFromCore.slave = ruby_system.network.master
648
649 rb_cntrl.responseFromCore = MessageBuffer()
650 rb_cntrl.responseFromCore.slave = ruby_system.network.master
651
652 rb_cntrl.requestToNetwork = MessageBuffer()
653 rb_cntrl.requestToNetwork.master = ruby_system.network.slave
654
655 rb_cntrl.notifyFromRegionDir = MessageBuffer()
656 rb_cntrl.notifyFromRegionDir.slave = ruby_system.network.master
657
658 rb_cntrl.probeFromRegionDir = MessageBuffer()
659 rb_cntrl.probeFromRegionDir.slave = ruby_system.network.master
660
661 rb_cntrl.unblockFromDir = MessageBuffer()
662 rb_cntrl.unblockFromDir.slave = ruby_system.network.master
663
664 rb_cntrl.responseToRegDir = MessageBuffer()
665 rb_cntrl.responseToRegDir.master = ruby_system.network.slave
666
667 rb_cntrl.triggerQueue = MessageBuffer(ordered = True)
668
669 tcc_cntrl.regionBufferNum = rb_cntrl.version
670
671 exec("system.tcc_cntrl%d = tcc_cntrl" % i)
672 exec("system.tcc_rb_cntrl%d = rb_cntrl" % i)
673
674 # TCC cntrls added to the GPU cluster
675 gpuCluster.add(tcc_cntrl)
676 gpuCluster.add(rb_cntrl)
677
678 # Because of wire buffers, num_l3caches must equal num_dirs
679 # Region coherence only works with 1 dir
680 assert(options.num_l3caches == options.num_dirs == 1)
681
682 # This is the base crossbar that connects the L3s, Dirs, and cpu/gpu
683 # Clusters
684 mainCluster = Cluster(intBW = crossbar_bw)
685
686 if options.numa_high_bit:
687 numa_bit = options.numa_high_bit
688 else:
689 # if the numa_bit is not specified, set the directory bits as the
690 # lowest bits above the block offset bits, and the numa_bit as the
691 # highest of those directory bits
692 dir_bits = int(math.log(options.num_dirs, 2))
693 block_size_bits = int(math.log(options.cacheline_size, 2))
694 numa_bit = block_size_bits + dir_bits - 1
695
696 dir_ranges = []
697 for r in system.mem_ranges:
698 addr_range = m5.objects.AddrRange(r.start, size = r.size(),
699 intlvHighBit = numa_bit,
700 intlvBits = dir_bits,
701 intlvMatch = i)
702 dir_ranges.append(addr_range)
703
704 dir_cntrl = DirCntrl()
705 dir_cntrl.create(options, dir_ranges, ruby_system, system)
706 dir_cntrl.number_of_TBEs = 2560 * options.num_compute_units
707 dir_cntrl.useL3OnWT = options.use_L3_on_WT
708
709 # Connect the Directory controller to the ruby network
710 dir_cntrl.requestFromCores = MessageBuffer()
711 dir_cntrl.requestFromCores.slave = ruby_system.network.master
712
713 dir_cntrl.responseFromCores = MessageBuffer()
714 dir_cntrl.responseFromCores.slave = ruby_system.network.master
715
716 dir_cntrl.unblockFromCores = MessageBuffer()
717 dir_cntrl.unblockFromCores.slave = ruby_system.network.master
718
719 dir_cntrl.probeToCore = MessageBuffer()
720 dir_cntrl.probeToCore.master = ruby_system.network.slave
721
722 dir_cntrl.responseToCore = MessageBuffer()
723 dir_cntrl.responseToCore.master = ruby_system.network.slave
724
725 dir_cntrl.reqFromRegBuf = MessageBuffer()
726 dir_cntrl.reqFromRegBuf.slave = ruby_system.network.master
727
728 dir_cntrl.reqToRegDir = MessageBuffer(ordered = True)
729 dir_cntrl.reqToRegDir.master = ruby_system.network.slave
730
731 dir_cntrl.reqFromRegDir = MessageBuffer(ordered = True)
732 dir_cntrl.reqFromRegDir.slave = ruby_system.network.master
733
734 dir_cntrl.unblockToRegDir = MessageBuffer()
735 dir_cntrl.unblockToRegDir.master = ruby_system.network.slave
736
737 dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
738 dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True)
739 dir_cntrl.requestToMemory = MessageBuffer()
740 dir_cntrl.responseFromMemory = MessageBuffer()
741
742 exec("system.dir_cntrl%d = dir_cntrl" % i)
743 dir_cntrl_nodes.append(dir_cntrl)
744
745 mainCluster.add(dir_cntrl)
746
747 reg_cntrl = RegionCntrl(noTCCdir=True,TCC_select_num_bits = TCC_bits)
748 reg_cntrl.create(options, ruby_system, system)
749 reg_cntrl.number_of_TBEs = options.num_tbes
750 reg_cntrl.cpuRegionBufferNum = system.rb_cntrl0.version
751 reg_cntrl.gpuRegionBufferNum = system.tcc_rb_cntrl0.version
752
753 # Connect the Region Dir controllers to the ruby network
754 reg_cntrl.requestToDir = MessageBuffer(ordered = True)
755 reg_cntrl.requestToDir.master = ruby_system.network.slave
756
757 reg_cntrl.notifyToRBuffer = MessageBuffer()
758 reg_cntrl.notifyToRBuffer.master = ruby_system.network.slave
759
760 reg_cntrl.probeToRBuffer = MessageBuffer()
761 reg_cntrl.probeToRBuffer.master = ruby_system.network.slave
762
763 reg_cntrl.responseFromRBuffer = MessageBuffer()
764 reg_cntrl.responseFromRBuffer.slave = ruby_system.network.master
765
766 reg_cntrl.requestFromRegBuf = MessageBuffer()
767 reg_cntrl.requestFromRegBuf.slave = ruby_system.network.master
768
769 reg_cntrl.triggerQueue = MessageBuffer(ordered = True)
770
771 exec("system.reg_cntrl%d = reg_cntrl" % i)
772
773 mainCluster.add(reg_cntrl)
774
775 # Assuming no DMA devices
776 assert(len(dma_devices) == 0)
777
778 # Add cpu/gpu clusters to main cluster
779 mainCluster.add(cpuCluster)
780 mainCluster.add(gpuCluster)
781
782 ruby_system.network.number_of_virtual_networks = 10
783
784 return (cpu_sequencers, dir_cntrl_nodes, mainCluster)