configs/ruby/MESI_CMP_directory.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # Copyright (c) 2009 Advanced Micro Devices, Inc.
   3 # All rights reserved.
   4 #
   5 # Redistribution and use in source and binary forms, with or without
   6 # modification, are permitted provided that the following conditions are
   7 # met: redistributions of source code must retain the above copyright
   8 # notice, this list of conditions and the following disclaimer;
   9 # redistributions in binary form must reproduce the above copyright
  10 # notice, this list of conditions and the following disclaimer in the
  11 # documentation and/or other materials provided with the distribution;
  12 # neither the name of the copyright holders nor the names of its
  13 # contributors may be used to endorse or promote products derived from
  14 # this software without specific prior written permission.
  15 #
  16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27 #
  28 # Authors: Brad Beckmann
  29
  30 import math
  31 import m5
  32 from m5.objects import *
  33 from m5.defines import buildEnv
  34
  35 #
  36 # Note: the L1 Cache latency is only used by the sequencer on fast path hits
  37 #
  38 class L1Cache(RubyCache):
  39     latency = 3
  40
  41 #
  42 # Note: the L2 Cache latency is not currently used
  43 #
  44 class L2Cache(RubyCache):
  45     latency = 15
  46
  47 def define_options(parser):
  48     return
  49
  50 def create_system(options, system, piobus, dma_devices, ruby_system):
  51
  52     if buildEnv['PROTOCOL'] != 'MESI_CMP_directory':
  53         panic("This script requires the MESI_CMP_directory protocol to be built.")
  54
  55     cpu_sequencers = []
  56
  57     #
  58     # The ruby network creation expects the list of nodes in the system to be
  59     # consistent with the NetDest list.  Therefore the l1 controller nodes must be
  60     # listed before the directory nodes and directory nodes before dma nodes, etc.
  61     #
  62     l1_cntrl_nodes = []
  63     l2_cntrl_nodes = []
  64     dir_cntrl_nodes = []
  65     dma_cntrl_nodes = []
  66
  67     #
  68     # Must create the individual controllers before the network to ensure the
  69     # controller constructors are called before the network constructor
  70     #
  71     l2_bits = int(math.log(options.num_l2caches, 2))
  72     block_size_bits = int(math.log(options.cacheline_size, 2))
  73
  74     cntrl_count = 0
  75
  76     for i in xrange(options.num_cpus):
  77         #
  78         # First create the Ruby objects associated with this cpu
  79         #
  80         l1i_cache = L1Cache(size = options.l1i_size,
  81                             assoc = options.l1i_assoc,
  82                             start_index_bit = block_size_bits)
  83         l1d_cache = L1Cache(size = options.l1d_size,
  84                             assoc = options.l1d_assoc,
  85                             start_index_bit = block_size_bits)
  86
  87         l1_cntrl = L1Cache_Controller(version = i,
  88                                       cntrl_id = cntrl_count,
  89                                       L1IcacheMemory = l1i_cache,
  90                                       L1DcacheMemory = l1d_cache,
  91                                       l2_select_num_bits = l2_bits,
  92                                       ruby_system = ruby_system)
  93
  94         cpu_seq = RubySequencer(version = i,
  95                                 icache = l1i_cache,
  96                                 dcache = l1d_cache,
  97                                 physMemPort = system.physmem.port,
  98                                 physmem = system.physmem,
  99                                 ruby_system = ruby_system)
 100
 101         l1_cntrl.sequencer = cpu_seq
 102
 103         if piobus != None:
 104             cpu_seq.pio_port = piobus.port
 105
 106         exec("system.l1_cntrl%d = l1_cntrl" % i)
 107
 108         #
 109         # Add controllers and sequencers to the appropriate lists
 110         #
 111         cpu_sequencers.append(cpu_seq)
 112         l1_cntrl_nodes.append(l1_cntrl)
 113
 114         cntrl_count += 1
 115
 116     l2_index_start = block_size_bits + l2_bits
 117
 118     for i in xrange(options.num_l2caches):
 119         #
 120         # First create the Ruby objects associated with this cpu
 121         #
 122         l2_cache = L2Cache(size = options.l2_size,
 123                            assoc = options.l2_assoc,
 124                            start_index_bit = l2_index_start)
 125
 126         l2_cntrl = L2Cache_Controller(version = i,
 127                                       cntrl_id = cntrl_count,
 128                                       L2cacheMemory = l2_cache,
 129                                       ruby_system = ruby_system)
 130
 131         exec("system.l2_cntrl%d = l2_cntrl" % i)
 132         l2_cntrl_nodes.append(l2_cntrl)
 133
 134         cntrl_count += 1
 135
 136     phys_mem_size = long(system.physmem.range.second) - \
 137                       long(system.physmem.range.first) + 1
 138     mem_module_size = phys_mem_size / options.num_dirs
 139
 140     for i in xrange(options.num_dirs):
 141         #
 142         # Create the Ruby objects associated with the directory controller
 143         #
 144
 145         mem_cntrl = RubyMemoryControl(version = i)
 146
 147         dir_size = MemorySize('0B')
 148         dir_size.value = mem_module_size
 149
 150         dir_cntrl = Directory_Controller(version = i,
 151                                          cntrl_id = cntrl_count,
 152                                          directory = \
 153                                          RubyDirectoryMemory(version = i,
 154                                                              size = dir_size),
 155                                          memBuffer = mem_cntrl,
 156                                          ruby_system = ruby_system)
 157
 158         exec("system.dir_cntrl%d = dir_cntrl" % i)
 159         dir_cntrl_nodes.append(dir_cntrl)
 160
 161         cntrl_count += 1
 162
 163     for i, dma_device in enumerate(dma_devices):
 164         #
 165         # Create the Ruby objects associated with the dma controller
 166         #
 167         dma_seq = DMASequencer(version = i,
 168                                physMemPort = system.physmem.port,
 169                                physmem = system.physmem)
 170
 171         dma_cntrl = DMA_Controller(version = i,
 172                                    cntrl_id = cntrl_count,
 173                                    dma_sequencer = dma_seq)
 174
 175         exec("system.dma_cntrl%d = dma_cntrl" % i)
 176         if dma_device.type == 'MemTest':
 177             exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
 178         else:
 179             exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
 180         dma_cntrl_nodes.append(dma_cntrl)
 181
 182         cntrl_count += 1
 183
 184     all_cntrls = l1_cntrl_nodes + \
 185                  l2_cntrl_nodes + \
 186                  dir_cntrl_nodes + \
 187                  dma_cntrl_nodes
 188
 189     return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)