1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
2 # Copyright (c) 2009 Advanced Micro Devices, Inc.
3 # Copyright (c) 2013 Mark D. Hill and David A. Wood
6 # Redistribution and use in source and binary forms, with or without
7 # modification, are permitted provided that the following conditions are
8 # met: redistributions of source code must retain the above copyright
9 # notice, this list of conditions and the following disclaimer;
10 # redistributions in binary form must reproduce the above copyright
11 # notice, this list of conditions and the following disclaimer in the
12 # documentation and/or other materials provided with the distribution;
13 # neither the name of the copyright holders nor the names of its
14 # contributors may be used to endorse or promote products derived from
15 # this software without specific prior written permission.
17 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 # Authors: Brad Beckmann
34 from m5
.objects
import *
35 from m5
.defines
import buildEnv
36 from Ruby
import create_topology
37 from Ruby
import send_evicts
40 # Note: the L1 Cache latency is only used by the sequencer on fast path hits
42 class L0Cache(RubyCache
):
45 class L1Cache(RubyCache
):
49 # Note: the L2 Cache latency is not currently used
51 class L2Cache(RubyCache
):
54 def define_options(parser
):
55 parser
.add_option("--num-clusters", type="int", default
=1,
56 help="number of clusters in a design in which there are shared\
57 caches private to clusters")
60 def create_system(options
, full_system
, system
, dma_ports
, ruby_system
):
62 if buildEnv
['PROTOCOL'] != 'MESI_Three_Level':
63 fatal("This script requires the MESI_Three_Level protocol to be built.")
68 # The ruby network creation expects the list of nodes in the system to be
69 # consistent with the NetDest list. Therefore the l1 controller nodes must be
70 # listed before the directory nodes and directory nodes before dma nodes, etc.
78 assert (options
.num_cpus
% options
.num_clusters
== 0)
79 num_cpus_per_cluster
= options
.num_cpus
/ options
.num_clusters
81 assert (options
.num_l2caches
% options
.num_clusters
== 0)
82 num_l2caches_per_cluster
= options
.num_l2caches
/ options
.num_clusters
84 l2_bits
= int(math
.log(num_l2caches_per_cluster
, 2))
85 block_size_bits
= int(math
.log(options
.cacheline_size
, 2))
86 l2_index_start
= block_size_bits
+ l2_bits
89 # Must create the individual controllers before the network to ensure the
90 # controller constructors are called before the network constructor
92 for i
in xrange(options
.num_clusters
):
93 for j
in xrange(num_cpus_per_cluster
):
95 # First create the Ruby objects associated with this cpu
97 l0i_cache
= L0Cache(size
= '4096B', assoc
= 1, is_icache
= True,
98 start_index_bit
= block_size_bits
,
99 replacement_policy
= LRUReplacementPolicy())
101 l0d_cache
= L0Cache(size
= '4096B', assoc
= 1, is_icache
= False,
102 start_index_bit
= block_size_bits
,
103 replacement_policy
= LRUReplacementPolicy())
105 l0_cntrl
= L0Cache_Controller(version
= i
*num_cpus_per_cluster
+ j
,
106 Icache
= l0i_cache
, Dcache
= l0d_cache
,
107 send_evictions
= send_evicts(options
),
108 clk_domain
=system
.cpu
[i
].clk_domain
,
109 ruby_system
= ruby_system
)
111 cpu_seq
= RubySequencer(version
= i
, icache
= l0i_cache
,
112 clk_domain
=system
.cpu
[i
].clk_domain
,
113 dcache
= l0d_cache
, ruby_system
= ruby_system
)
115 l0_cntrl
.sequencer
= cpu_seq
117 l1_cache
= L1Cache(size
= options
.l1d_size
, assoc
= options
.l1d_assoc
,
118 start_index_bit
= block_size_bits
, is_icache
= False)
120 l1_cntrl
= L1Cache_Controller(version
= i
*num_cpus_per_cluster
+j
,
121 cache
= l1_cache
, l2_select_num_bits
= l2_bits
,
122 cluster_id
= i
, ruby_system
= ruby_system
)
124 exec("ruby_system.l0_cntrl%d = l0_cntrl" % (
125 i
*num_cpus_per_cluster
+j
))
126 exec("ruby_system.l1_cntrl%d = l1_cntrl" % (
127 i
*num_cpus_per_cluster
+j
))
130 # Add controllers and sequencers to the appropriate lists
132 cpu_sequencers
.append(cpu_seq
)
133 l0_cntrl_nodes
.append(l0_cntrl
)
134 l1_cntrl_nodes
.append(l1_cntrl
)
136 # Connect the L0 and L1 controllers
137 l0_cntrl
.bufferToL1
= l1_cntrl
.bufferFromL0
138 l0_cntrl
.bufferFromL1
= l1_cntrl
.bufferToL0
140 # Connect the L1 controllers and the network
141 l1_cntrl
.requestToL2
= ruby_system
.network
.slave
142 l1_cntrl
.responseToL2
= ruby_system
.network
.slave
143 l1_cntrl
.unblockToL2
= ruby_system
.network
.slave
145 l1_cntrl
.requestFromL2
= ruby_system
.network
.master
146 l1_cntrl
.responseFromL2
= ruby_system
.network
.master
149 for j
in xrange(num_l2caches_per_cluster
):
150 l2_cache
= L2Cache(size
= options
.l2_size
,
151 assoc
= options
.l2_assoc
,
152 start_index_bit
= l2_index_start
)
154 l2_cntrl
= L2Cache_Controller(
155 version
= i
* num_l2caches_per_cluster
+ j
,
156 L2cache
= l2_cache
, cluster_id
= i
,
157 transitions_per_cycle
=options
.ports
,
158 ruby_system
= ruby_system
)
160 exec("ruby_system.l2_cntrl%d = l2_cntrl" % (
161 i
* num_l2caches_per_cluster
+ j
))
162 l2_cntrl_nodes
.append(l2_cntrl
)
164 # Connect the L2 controllers and the network
165 l2_cntrl
.DirRequestFromL2Cache
= ruby_system
.network
.slave
166 l2_cntrl
.L1RequestFromL2Cache
= ruby_system
.network
.slave
167 l2_cntrl
.responseFromL2Cache
= ruby_system
.network
.slave
169 l2_cntrl
.unblockToL2Cache
= ruby_system
.network
.master
170 l2_cntrl
.L1RequestToL2Cache
= ruby_system
.network
.master
171 l2_cntrl
.responseToL2Cache
= ruby_system
.network
.master
173 phys_mem_size
= sum(map(lambda r
: r
.size(), system
.mem_ranges
))
174 assert(phys_mem_size
% options
.num_dirs
== 0)
175 mem_module_size
= phys_mem_size
/ options
.num_dirs
177 # Run each of the ruby memory controllers at a ratio of the frequency of
179 # clk_divider value is a fix to pass regression.
180 ruby_system
.memctrl_clk_domain
= DerivedClockDomain(
181 clk_domain
=ruby_system
.clk_domain
,
184 for i
in xrange(options
.num_dirs
):
186 # Create the Ruby objects associated with the directory controller
188 dir_size
= MemorySize('0B')
189 dir_size
.value
= mem_module_size
191 dir_cntrl
= Directory_Controller(version
= i
,
192 directory
= RubyDirectoryMemory(
193 version
= i
, size
= dir_size
),
194 transitions_per_cycle
= options
.ports
,
195 ruby_system
= ruby_system
)
197 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i
)
198 dir_cntrl_nodes
.append(dir_cntrl
)
200 # Connect the directory controllers and the network
201 dir_cntrl
.requestToDir
= ruby_system
.network
.master
202 dir_cntrl
.responseToDir
= ruby_system
.network
.master
203 dir_cntrl
.responseFromDir
= ruby_system
.network
.slave
205 for i
, dma_port
in enumerate(dma_ports
):
207 # Create the Ruby objects associated with the dma controller
209 dma_seq
= DMASequencer(version
= i
,
210 ruby_system
= ruby_system
)
212 dma_cntrl
= DMA_Controller(version
= i
,
213 dma_sequencer
= dma_seq
,
214 transitions_per_cycle
= options
.ports
,
215 ruby_system
= ruby_system
)
217 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i
)
218 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i
)
219 dma_cntrl_nodes
.append(dma_cntrl
)
221 # Connect the dma controller to the network
222 dma_cntrl
.responseFromDir
= ruby_system
.network
.master
223 dma_cntrl
.requestToDir
= ruby_system
.network
.slave
225 all_cntrls
= l0_cntrl_nodes
+ \
231 # Create the io controller and the sequencer
233 io_seq
= DMASequencer(version
=len(dma_ports
), ruby_system
=ruby_system
)
234 ruby_system
._io
_port
= io_seq
235 io_controller
= DMA_Controller(version
= len(dma_ports
),
236 dma_sequencer
= io_seq
,
237 ruby_system
= ruby_system
)
238 ruby_system
.io_controller
= io_controller
240 # Connect the dma controller to the network
241 io_controller
.responseFromDir
= ruby_system
.network
.master
242 io_controller
.requestToDir
= ruby_system
.network
.slave
244 all_cntrls
= all_cntrls
+ [io_controller
]
246 topology
= create_topology(all_cntrls
, options
)
247 return (cpu_sequencers
, dir_cntrl_nodes
, topology
)