1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
2 # Copyright (c) 2009 Advanced Micro Devices, Inc.
5 # Redistribution and use in source and binary forms, with or without
6 # modification, are permitted provided that the following conditions are
7 # met: redistributions of source code must retain the above copyright
8 # notice, this list of conditions and the following disclaimer;
9 # redistributions in binary form must reproduce the above copyright
10 # notice, this list of conditions and the following disclaimer in the
11 # documentation and/or other materials provided with the distribution;
12 # neither the name of the copyright holders nor the names of its
13 # contributors may be used to endorse or promote products derived from
14 # this software without specific prior written permission.
16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 # Authors: Brad Beckmann
32 from m5
.objects
import *
33 from m5
.defines
import buildEnv
34 from Ruby
import create_topology
35 from Ruby
import send_evicts
38 # Declare caches used by the protocol
40 class L1Cache(RubyCache
): pass
41 class L2Cache(RubyCache
): pass
43 def define_options(parser
):
46 def create_system(options
, full_system
, system
, dma_ports
, ruby_system
):
48 if buildEnv
['PROTOCOL'] != 'MESI_Two_Level':
49 fatal("This script requires the MESI_Two_Level protocol to be built.")
54 # The ruby network creation expects the list of nodes in the system to be
55 # consistent with the NetDest list. Therefore the l1 controller nodes must be
56 # listed before the directory nodes and directory nodes before dma nodes, etc.
64 # Must create the individual controllers before the network to ensure the
65 # controller constructors are called before the network constructor
67 l2_bits
= int(math
.log(options
.num_l2caches
, 2))
68 block_size_bits
= int(math
.log(options
.cacheline_size
, 2))
70 for i
in xrange(options
.num_cpus
):
72 # First create the Ruby objects associated with this cpu
74 l1i_cache
= L1Cache(size
= options
.l1i_size
,
75 assoc
= options
.l1i_assoc
,
76 start_index_bit
= block_size_bits
,
78 l1d_cache
= L1Cache(size
= options
.l1d_size
,
79 assoc
= options
.l1d_assoc
,
80 start_index_bit
= block_size_bits
,
83 prefetcher
= RubyPrefetcher
.Prefetcher()
85 l1_cntrl
= L1Cache_Controller(version
= i
,
88 l2_select_num_bits
= l2_bits
,
89 send_evictions
= send_evicts(options
),
90 prefetcher
= prefetcher
,
91 ruby_system
= ruby_system
,
92 clk_domain
=system
.cpu
[i
].clk_domain
,
93 transitions_per_cycle
=options
.ports
,
94 enable_prefetch
= False)
96 cpu_seq
= RubySequencer(version
= i
,
99 clk_domain
=system
.cpu
[i
].clk_domain
,
100 ruby_system
= ruby_system
)
102 l1_cntrl
.sequencer
= cpu_seq
103 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i
)
105 # Add controllers and sequencers to the appropriate lists
106 cpu_sequencers
.append(cpu_seq
)
107 l1_cntrl_nodes
.append(l1_cntrl
)
109 # Connect the L1 controllers and the network
110 l1_cntrl
.mandatoryQueue
= MessageBuffer()
111 l1_cntrl
.requestFromL1Cache
= MessageBuffer()
112 l1_cntrl
.requestFromL1Cache
.master
= ruby_system
.network
.slave
113 l1_cntrl
.responseFromL1Cache
= MessageBuffer()
114 l1_cntrl
.responseFromL1Cache
.master
= ruby_system
.network
.slave
115 l1_cntrl
.unblockFromL1Cache
= MessageBuffer()
116 l1_cntrl
.unblockFromL1Cache
.master
= ruby_system
.network
.slave
118 l1_cntrl
.optionalQueue
= MessageBuffer()
120 l1_cntrl
.requestToL1Cache
= MessageBuffer()
121 l1_cntrl
.requestToL1Cache
.slave
= ruby_system
.network
.master
122 l1_cntrl
.responseToL1Cache
= MessageBuffer()
123 l1_cntrl
.responseToL1Cache
.slave
= ruby_system
.network
.master
126 l2_index_start
= block_size_bits
+ l2_bits
128 for i
in xrange(options
.num_l2caches
):
130 # First create the Ruby objects associated with this cpu
132 l2_cache
= L2Cache(size
= options
.l2_size
,
133 assoc
= options
.l2_assoc
,
134 start_index_bit
= l2_index_start
)
136 l2_cntrl
= L2Cache_Controller(version
= i
,
138 transitions_per_cycle
=options
.ports
,
139 ruby_system
= ruby_system
)
141 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i
)
142 l2_cntrl_nodes
.append(l2_cntrl
)
144 # Connect the L2 controllers and the network
145 l2_cntrl
.DirRequestFromL2Cache
= MessageBuffer()
146 l2_cntrl
.DirRequestFromL2Cache
.master
= ruby_system
.network
.slave
147 l2_cntrl
.L1RequestFromL2Cache
= MessageBuffer()
148 l2_cntrl
.L1RequestFromL2Cache
.master
= ruby_system
.network
.slave
149 l2_cntrl
.responseFromL2Cache
= MessageBuffer()
150 l2_cntrl
.responseFromL2Cache
.master
= ruby_system
.network
.slave
152 l2_cntrl
.unblockToL2Cache
= MessageBuffer()
153 l2_cntrl
.unblockToL2Cache
.slave
= ruby_system
.network
.master
154 l2_cntrl
.L1RequestToL2Cache
= MessageBuffer()
155 l2_cntrl
.L1RequestToL2Cache
.slave
= ruby_system
.network
.master
156 l2_cntrl
.responseToL2Cache
= MessageBuffer()
157 l2_cntrl
.responseToL2Cache
.slave
= ruby_system
.network
.master
160 phys_mem_size
= sum(map(lambda r
: r
.size(), system
.mem_ranges
))
161 assert(phys_mem_size
% options
.num_dirs
== 0)
162 mem_module_size
= phys_mem_size
/ options
.num_dirs
165 # Run each of the ruby memory controllers at a ratio of the frequency of
167 # clk_divider value is a fix to pass regression.
168 ruby_system
.memctrl_clk_domain
= DerivedClockDomain(
169 clk_domain
=ruby_system
.clk_domain
,
172 for i
in xrange(options
.num_dirs
):
173 dir_size
= MemorySize('0B')
174 dir_size
.value
= mem_module_size
176 dir_cntrl
= Directory_Controller(version
= i
,
177 directory
= RubyDirectoryMemory(
178 version
= i
, size
= dir_size
),
179 transitions_per_cycle
= options
.ports
,
180 ruby_system
= ruby_system
)
182 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i
)
183 dir_cntrl_nodes
.append(dir_cntrl
)
185 # Connect the directory controllers and the network
186 dir_cntrl
.requestToDir
= MessageBuffer()
187 dir_cntrl
.requestToDir
.slave
= ruby_system
.network
.master
188 dir_cntrl
.responseToDir
= MessageBuffer()
189 dir_cntrl
.responseToDir
.slave
= ruby_system
.network
.master
190 dir_cntrl
.responseFromDir
= MessageBuffer()
191 dir_cntrl
.responseFromDir
.master
= ruby_system
.network
.slave
192 dir_cntrl
.responseFromMemory
= MessageBuffer()
195 for i
, dma_port
in enumerate(dma_ports
):
196 # Create the Ruby objects associated with the dma controller
197 dma_seq
= DMASequencer(version
= i
,
198 ruby_system
= ruby_system
,
201 dma_cntrl
= DMA_Controller(version
= i
,
202 dma_sequencer
= dma_seq
,
203 transitions_per_cycle
= options
.ports
,
204 ruby_system
= ruby_system
)
206 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i
)
207 dma_cntrl_nodes
.append(dma_cntrl
)
209 # Connect the dma controller to the network
210 dma_cntrl
.mandatoryQueue
= MessageBuffer()
211 dma_cntrl
.responseFromDir
= MessageBuffer(ordered
= True)
212 dma_cntrl
.responseFromDir
.slave
= ruby_system
.network
.master
213 dma_cntrl
.requestToDir
= MessageBuffer()
214 dma_cntrl
.requestToDir
.master
= ruby_system
.network
.slave
216 all_cntrls
= l1_cntrl_nodes
+ \
221 # Create the io controller and the sequencer
223 io_seq
= DMASequencer(version
=len(dma_ports
), ruby_system
=ruby_system
)
224 ruby_system
._io
_port
= io_seq
225 io_controller
= DMA_Controller(version
= len(dma_ports
),
226 dma_sequencer
= io_seq
,
227 ruby_system
= ruby_system
)
228 ruby_system
.io_controller
= io_controller
230 # Connect the dma controller to the network
231 io_controller
.mandatoryQueue
= MessageBuffer()
232 io_controller
.responseFromDir
= MessageBuffer(ordered
= True)
233 io_controller
.responseFromDir
.slave
= ruby_system
.network
.master
234 io_controller
.requestToDir
= MessageBuffer()
235 io_controller
.requestToDir
.master
= ruby_system
.network
.slave
237 all_cntrls
= all_cntrls
+ [io_controller
]
239 topology
= create_topology(all_cntrls
, options
)
240 return (cpu_sequencers
, dir_cntrl_nodes
, topology
)